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This pull request introduces a new SystemRDL-based register interface and target module for the HWPE controller, modernizing the register file integration and deprecating the legacy register file modules (which are kept available). The changes provide a reference SystemRDL description, a script for generating register interface artifacts, and a new hwpe_ctrl_target module designed to work with the generated interface. The Bender configuration is updated to use these new files and move legacy files to a deprecated directory.
This new register interface has been tested in NEureka (feature branch here: https://github.com/pulp-platform/neureka/tree/fc/rdl).

SystemRDL-based Register Interface Integration:

  • Added a reference SystemRDL register map in hwpe_ctrl_regif_example.rdl to define the HWPE control port's mandatory and customizable registers.
  • Added a script rdl.sh to generate SystemVerilog, HTML, and C header files from the SystemRDL file using PeakRDL, and to patch the generated structs for compatibility.

New Target Module:

  • Introduced the hwpe_ctrl_target.sv module, which implements a target port compatible with SystemRDL-generated register files, replacing the deprecated hwpe_ctrl_slave. This module handles job queueing, soft clear, and register interfacing, and is designed for easy integration with custom register sets.

Project Configuration Updates:

  • Updated Bender.yml to reference the new SystemRDL-based files and move legacy register file modules to a deprecated directory, ensuring new designs use the modernized flow.

@FrancescoConti FrancescoConti changed the title Fc/rdl SystemRDL-based register interface for HWPE controller Dec 23, 2025
@FrancescoConti FrancescoConti self-assigned this Dec 23, 2025
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Pull request overview

This pull request modernizes the HWPE controller register interface by introducing a SystemRDL-based approach that replaces the legacy manual register file implementation. The changes include a reference SystemRDL description defining mandatory and customizable registers, a code generation script using PeakRDL, and a new hwpe_ctrl_target module compatible with generated register interfaces. Legacy modules are preserved in a deprecated directory for backward compatibility.

Key changes:

  • Added SystemRDL-based register interface generation workflow (.rdl file + generation script)
  • Introduced new hwpe_ctrl_target.sv module for SystemRDL-generated register file integration
  • Moved legacy register file modules (hwpe_ctrl_slave, hwpe_ctrl_regfile*) to deprecated/ directory

Reviewed changes

Copilot reviewed 4 out of 9 changed files in this pull request and generated 10 comments.

Show a summary per file
File Description
rtl/rdl.sh Shell script for generating SystemVerilog, HTML, and C header files from SystemRDL using PeakRDL
rtl/hwpe_ctrl_regif_example.rdl Reference SystemRDL description defining mandatory HWPE control registers and example register sets
rtl/hwpe_ctrl_target.sv New target module implementing job queueing and soft clear with SystemRDL register interface
rtl/deprecated/hwpe_ctrl_slave.sv Legacy slave module moved to deprecated directory
rtl/deprecated/hwpe_ctrl_regfile*.sv Legacy register file implementation modules moved to deprecated directory
Bender.yml Updated build configuration to reference new files and deprecated directory paths

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FrancescoConti and others added 4 commits December 23, 2025 12:36
Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com>
Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com>
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Very cool to see SystemRDL getting more adoption🤓

I can't comment on the logic itself, but I can maybe give some feedback on SystemRDL. There is an official SystemRDL style guide, which you are already following mostly, except for the prefixes. The nice thing about SystemRDL is that it is a hierarchical language and its not possible to create naming collisions! So you can generally lose the hpwe_ prefixes everywhere inside the addrmap (which already has it). Then, the names and types also become a lot shorter, which makes the SystemVerilog code a bit nicer.

But other than that, it looks very clean!

desc = "Control register map for the HWPE, including mandatory control/status registers and example job-independent and job-dependent configuration registers.";

// Mandatory COMMIT_TRIGGER register. Not to be updated inside HWPEs.
reg hwpe_commit_trigger {

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You can remove the hwpe_ prefix here

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Good point. I will fix this.

hw = w;
sw = r;
swacc = true;
} acquire[31:0] = 0;

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This is a bit annoying in SystemRDL that you need to create a field container in reg, even if it uses the full regwidth. Because then accessing it requires hwpe_acquire.acquire, which feels a bit redundant. One way to (slightly) improve this is to call the the reg by its name i.e. acquire and then the field just value or val.

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Makes sense. I will do that.

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3 participants