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Jg support #2

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fac1a54
Aligned to changes in Vincent Vega
FrancescoConti Feb 12, 2019
4ff1949
Add parameters in IP yml description for JG EDA tool
florent-gwt Sep 9, 2019
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18 changes: 9 additions & 9 deletions rtl/low_latency_interco/ArbitrationTree.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -154,19 +154,19 @@ module ArbitrationTree
//// ---------------------------------------------------------------------- ////
//// ------- REQ ARBITRATION TREE WIRES ----------- ////
//// ---------------------------------------------------------------------- ////
logic [DATA_WIDTH-1:0] data_wdata_LEVEL[N_WIRE-1:0];
logic [ADDR_WIDTH-1:0] data_add_LEVEL[N_WIRE-1:0];
logic data_req_LEVEL[N_WIRE-1:0];
logic data_wen_LEVEL[N_WIRE-1:0];
logic [ID_WIDTH-1:0] data_ID_LEVEL[N_WIRE-1:0];
logic [N_WIRE-1:0][DATA_WIDTH-1:0] data_wdata_LEVEL;
logic [N_WIRE-1:0][ADDR_WIDTH-1:0] data_add_LEVEL;
logic [N_WIRE-1:0] data_req_LEVEL;
logic [N_WIRE-1:0] data_wen_LEVEL;
logic [N_WIRE-1:0][ID_WIDTH-1:0] data_ID_LEVEL;

logic [LOG_MASTER-1:0] ID_LEVEL[N_WIRE-1:0];
logic [N_WIRE-1:0][LOG_MASTER-1:0] ID_LEVEL;

logic [BE_WIDTH-1:0] data_be_LEVEL[N_WIRE-1:0];
logic [N_WIRE-1:0][BE_WIDTH-1:0] data_be_LEVEL;
`ifdef GNT_BASED_FC
logic data_gnt_LEVEL[N_WIRE-1:0];
logic [N_WIRE-1:0] data_gnt_LEVEL;
`else
logic data_stall_LEVEL[N_WIRE-1:0];
logic [N_WIRE-1:0] data_stall_LEVEL;
`endif


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4 changes: 2 additions & 2 deletions rtl/low_latency_interco/ResponseTree.sv
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Expand Up @@ -67,8 +67,8 @@ module ResponseTree

generate

logic [DATA_WIDTH-1:0] data_r_rdata_LEVEL[N_WIRE-1:0];
logic data_r_valid_LEVEL[N_WIRE-1:0];
logic [N_WIRE-1:0][DATA_WIDTH-1:0] data_r_rdata_LEVEL;
logic [N_WIRE-1:0] data_r_valid_LEVEL;

for(j=0; j < LOG_SLAVE; j++) // Iteration for the number of the stages minus one
begin : STAGE
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38 changes: 27 additions & 11 deletions rtl/peripheral_interco/AddressDecoder_PE_Req.sv
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Expand Up @@ -33,6 +33,7 @@
// Revision: //
// Revision v0.1 - File Created //
// Revision v0.2 - Code Restyling (19/02/2015) //
// v0.4 20/04/2018 - Supporting non power of 2 N_SLAVE //
// //
// Additional Comments: //
// //
Expand All @@ -42,7 +43,7 @@
////////////////////////////////////////////////////////////////////////////////

`include "parameters.v"
`include "pulp_soc_defines.sv"
`include "ulpsoc_defines.sv"

module AddressDecoder_PE_Req
#(
Expand Down Expand Up @@ -96,22 +97,37 @@ module AddressDecoder_PE_Req
`else
if( ( data_add_i[31:20] >= PE_START ) && ( data_add_i[31:20] < PE_END ) )
`endif
ROUTING_ADDR = data_add_i[PE_ROUTING_MSB:PE_ROUTING_LSB];
else
ROUTING_ADDR = '1;
ROUTING_ADDR = data_add_i[PE_ROUTING_MSB:PE_ROUTING_LSB];
else
ROUTING_ADDR = '1;
end

always_comb
begin : Combinational_ADDR_DEC_REQ
//DEFAULT VALUES
data_req_o = '0;

// Apply the rigth value
data_req_o[ROUTING_ADDR] = data_req_i;
`ifdef GNT_BASED_FC
data_gnt_o = data_gnt_i[ROUTING_ADDR];
`else
data_stall_o = data_stall_i[ROUTING_ADDR];
`endif
if(ROUTING_ADDR >= N_SLAVE-1)
begin
data_req_o[N_SLAVE-1] = data_req_i;

`ifdef GNT_BASED_FC
data_gnt_o = data_gnt_i[N_SLAVE-1];
`else
data_stall_o = data_stall_i[N_SLAVE-1];
`endif

end
else
begin
data_req_o[ROUTING_ADDR] = data_req_i;
`ifdef GNT_BASED_FC
data_gnt_o = data_gnt_i[ROUTING_ADDR];
`else
data_stall_o = data_stall_i[ROUTING_ADDR];
`endif
end
end

endmodule
227 changes: 114 additions & 113 deletions rtl/peripheral_interco/ArbitrationTree_PE.sv
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24 changes: 12 additions & 12 deletions rtl/peripheral_interco/RequestBlock2CH_PE.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -292,12 +292,12 @@ module RequestBlock2CH_PE
begin : CH0_ARB_TREE
ArbitrationTree_PE
#(
.ADDR_WIDTH ( ADDR_WIDTH ),
.ID_WIDTH ( ID_WIDTH ),
.N_MASTER ( N_CH0 ),
.DATA_WIDTH ( DATA_WIDTH ),
.BE_WIDTH ( BE_WIDTH ),
.MAX_COUNT ( N_CH0 - 1 )
.ADDR_WIDTH ( ADDR_WIDTH ),
.ID_WIDTH ( ID_WIDTH ),
.N_MASTER ( 2**$clog2(N_CH0) ),
.DATA_WIDTH ( DATA_WIDTH ),
.BE_WIDTH ( BE_WIDTH ),
.MAX_COUNT ( N_CH0 - 1 )
)
i_ArbitrationTree_PE
(
Expand Down Expand Up @@ -334,12 +334,12 @@ module RequestBlock2CH_PE
begin : CH1_ARB_TREE
ArbitrationTree_PE
#(
.ADDR_WIDTH ( ADDR_WIDTH ),
.ID_WIDTH ( ID_WIDTH ),
.N_MASTER ( N_CH1 ),
.DATA_WIDTH ( DATA_WIDTH ),
.BE_WIDTH ( BE_WIDTH ),
.MAX_COUNT ( N_CH1 - 1 )
.ADDR_WIDTH ( ADDR_WIDTH ),
.ID_WIDTH ( ID_WIDTH ),
.N_MASTER ( 2**$clog2(N_CH1) ),
.DATA_WIDTH ( DATA_WIDTH ),
.BE_WIDTH ( BE_WIDTH ),
.MAX_COUNT ( N_CH1 - 1 )
)
i_ArbitrationTree_PE
(
Expand Down
52 changes: 48 additions & 4 deletions rtl/peripheral_interco/ResponseBlock_PE.sv
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Expand Up @@ -32,6 +32,7 @@
// Revision v0.1 02/07/2011 - File Created //
// v0.2 15/08/2012 - Improved the Interface Structure, //
// Changed the routing mechanism //
// v0.4 20/04/2018 - Supporting non power of 2 N_SLAVE //
// //
// Additional Comments: //
// //
Expand Down Expand Up @@ -95,19 +96,62 @@ module ResponseBlock_PE
);


// Response channel exploded to powr of 2 inputs
logic [2**$clog2(N_SLAVE)-1:0] data_r_valid_int;
logic [2**$clog2(N_SLAVE)-1:0][DATA_WIDTH-1:0] data_r_rdata_int;
logic [2**$clog2(N_SLAVE)-1:0] data_r_opc_int;



genvar i;

generate
if(2**$clog2(N_SLAVE) == N_SLAVE)
begin : EXACT_POW2

for(i=0;i<N_SLAVE;i++)
begin
assign data_r_valid_int[i] = data_r_valid_i[i];
assign data_r_rdata_int[i] = data_r_rdata_i[i];
assign data_r_opc_int[i] = data_r_opc_i[i];
end

end
else
begin : NOT_POW2

for(i=0; i<2**$clog2(N_SLAVE); i++)
begin
if(i<N_SLAVE)
begin
assign data_r_valid_int[i] = data_r_valid_i[i];
assign data_r_rdata_int[i] = data_r_rdata_i[i];
assign data_r_opc_int[i] = data_r_opc_i[i];
end
else
begin
assign data_r_valid_int[i] = 1'b0;
assign data_r_rdata_int[i] = '0;
assign data_r_opc_int[i] = 1'b0;
end
end

end
endgenerate


// Response Tree
ResponseTree_PE
#(
.N_SLAVE(N_SLAVE),
.N_SLAVE( 2**$clog2(N_SLAVE) ),
.DATA_WIDTH(DATA_WIDTH)
)
i_ResponseTree_PE
(
// Response Input Channel
.data_r_valid_i(data_r_valid_i),
.data_r_rdata_i(data_r_rdata_i),
.data_r_opc_i(data_r_opc_i),
.data_r_valid_i(data_r_valid_int),
.data_r_rdata_i(data_r_rdata_int),
.data_r_opc_i(data_r_opc_int),
// Response Output Channel
.data_r_valid_o(data_r_valid_o),
.data_r_rdata_o(data_r_rdata_o),
Expand Down
66 changes: 34 additions & 32 deletions rtl/peripheral_interco/ResponseTree_PE.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -35,6 +35,8 @@
// Revision v0.1 02/07/2011 - File Created //
// v0.2 15/08/2012 - Improved the Interface Structure, //
// Changed the routing mechanism //
// Revision v0.3 - Improved identation (19/04/2018) //
// //
// Additional Comments: //
// //
// //
Expand Down Expand Up @@ -82,8 +84,8 @@ module ResponseTree_PE
.data_r_rdata1_i ( data_r_rdata_i[1] ),
.data_r_valid0_i ( data_r_valid_i[0] ),
.data_r_valid1_i ( data_r_valid_i[1] ),
.data_r_opc0_i ( data_r_opc_i[0] ),
.data_r_opc1_i ( data_r_opc_i[1] ),
.data_r_opc0_i ( data_r_opc_i [0] ),
.data_r_opc1_i ( data_r_opc_i [1] ),
// LEFT SIDE
.data_r_rdata_o ( data_r_rdata_o ),
.data_r_valid_o ( data_r_valid_o ),
Expand All @@ -95,9 +97,9 @@ module ResponseTree_PE
//// ---------------------------------------------------------------------- ////
//// ------- REQ ARBITRATION TREE WIRES ----------- ////
//// ---------------------------------------------------------------------- ////
logic [DATA_WIDTH-1:0] data_r_rdata_LEVEL[N_WIRE-1:0];
logic data_r_valid_LEVEL[N_WIRE-1:0];
logic data_r_opc_LEVEL[N_WIRE-1:0];
logic [N_WIRE-1:0][DATA_WIDTH-1:0] data_r_rdata_LEVEL;
logic [N_WIRE-1:0] data_r_valid_LEVEL;
logic [N_WIRE-1:0] data_r_opc_LEVEL;

for(j=0; j < LOG_SLAVE; j++) // Iteration for the number of the stages minus one
begin : STAGE
Expand All @@ -113,16 +115,16 @@ module ResponseTree_PE
i_FanInPrimitive_PE_Resp
(
// RIGTH SIDE
.data_r_rdata0_i(data_r_rdata_LEVEL[2*k]),
.data_r_rdata1_i(data_r_rdata_LEVEL[2*k+1]),
.data_r_valid0_i(data_r_valid_LEVEL[2*k]),
.data_r_valid1_i(data_r_valid_LEVEL[2*k+1]),
.data_r_opc0_i(data_r_opc_LEVEL[2*k]),
.data_r_opc1_i(data_r_opc_LEVEL[2*k+1]),
.data_r_rdata0_i ( data_r_rdata_LEVEL [2*k] ),
.data_r_rdata1_i ( data_r_rdata_LEVEL [2*k+1] ),
.data_r_valid0_i ( data_r_valid_LEVEL [2*k] ),
.data_r_valid1_i ( data_r_valid_LEVEL [2*k+1] ),
.data_r_opc0_i ( data_r_opc_LEVEL [2*k] ),
.data_r_opc1_i ( data_r_opc_LEVEL [2*k+1] ),
// RIGTH SIDE
.data_r_rdata_o(data_r_rdata_o),
.data_r_valid_o(data_r_valid_o),
.data_r_opc_o(data_r_opc_o)
.data_r_rdata_o ( data_r_rdata_o ),
.data_r_valid_o ( data_r_valid_o ),
.data_r_opc_o ( data_r_opc_o )
);
end
else if ( j < LOG_SLAVE - 1) // Middle Nodes
Expand All @@ -134,16 +136,16 @@ module ResponseTree_PE
i_FanInPrimitive_PE_Resp
(
// RIGTH SIDE
.data_r_rdata0_i(data_r_rdata_LEVEL[((2**j)*2-2) + 2*k]),
.data_r_rdata1_i(data_r_rdata_LEVEL[((2**j)*2-2) + 2*k +1]),
.data_r_valid0_i(data_r_valid_LEVEL[((2**j)*2-2) + 2*k]),
.data_r_valid1_i(data_r_valid_LEVEL[((2**j)*2-2) + 2*k+1]),
.data_r_opc0_i(data_r_opc_LEVEL[((2**j)*2-2) + 2*k]),
.data_r_opc1_i(data_r_opc_LEVEL[((2**j)*2-2) + 2*k+1]),
.data_r_rdata0_i ( data_r_rdata_LEVEL [((2**j)*2-2) + 2*k] ),
.data_r_rdata1_i ( data_r_rdata_LEVEL [((2**j)*2-2) + 2*k +1] ),
.data_r_valid0_i ( data_r_valid_LEVEL [((2**j)*2-2) + 2*k] ),
.data_r_valid1_i ( data_r_valid_LEVEL [((2**j)*2-2) + 2*k+1] ),
.data_r_opc0_i ( data_r_opc_LEVEL [((2**j)*2-2) + 2*k] ),
.data_r_opc1_i ( data_r_opc_LEVEL [((2**j)*2-2) + 2*k+1] ),
// LEFT SIDE
.data_r_rdata_o(data_r_rdata_LEVEL[((2**(j-1))*2-2) + k]),
.data_r_valid_o(data_r_valid_LEVEL[((2**(j-1))*2-2) + k]),
.data_r_opc_o(data_r_opc_LEVEL[((2**(j-1))*2-2) + k])
.data_r_rdata_o ( data_r_rdata_LEVEL [((2**(j-1))*2-2) + k] ),
.data_r_valid_o ( data_r_valid_LEVEL [((2**(j-1))*2-2) + k] ),
.data_r_opc_o ( data_r_opc_LEVEL [((2**(j-1))*2-2) + k] )
);
end // END of MIDDLE LEVELS Nodes
else // First stage (connected with the Main inputs ) --> ( j == N_SLAVE - 1 )
Expand All @@ -155,16 +157,16 @@ module ResponseTree_PE
i_FanInPrimitive_PE_Resp
(
// RIGTH SIDE
.data_r_rdata0_i(data_r_rdata_i[2*k]),
.data_r_rdata1_i(data_r_rdata_i[2*k+1]),
.data_r_valid0_i(data_r_valid_i[2*k]),
.data_r_valid1_i(data_r_valid_i[2*k+1]),
.data_r_opc0_i(data_r_opc_i[2*k]),
.data_r_opc1_i(data_r_opc_i[2*k+1]),
.data_r_rdata0_i ( data_r_rdata_i[2*k] ),
.data_r_rdata1_i ( data_r_rdata_i[2*k+1] ),
.data_r_valid0_i ( data_r_valid_i[2*k] ),
.data_r_valid1_i ( data_r_valid_i[2*k+1] ),
.data_r_opc0_i ( data_r_opc_i [2*k] ),
.data_r_opc1_i ( data_r_opc_i [2*k+1] ),
// LEFT SIDE
.data_r_rdata_o(data_r_rdata_LEVEL[((2**(j-1))*2-2) + k]),
.data_r_valid_o(data_r_valid_LEVEL[((2**(j-1))*2-2) + k]),
.data_r_opc_o(data_r_opc_LEVEL[((2**(j-1))*2-2) + k])
.data_r_rdata_o ( data_r_rdata_LEVEL [((2**(j-1))*2-2) + k] ),
.data_r_valid_o ( data_r_valid_LEVEL [((2**(j-1))*2-2) + k] ),
.data_r_opc_o ( data_r_opc_LEVEL [((2**(j-1))*2-2) + k] )
);
end // End of FIRST LEVEL Nodes (LEAF)
end
Expand Down
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