WIP: Multi-tile configuration of CachePool

Bender.lock

@@ -71,7 +71,7 @@ packages:
     - common_verification
     - register_interface
   insitu-cache:
-    revision: 04f72a7ac7e9091f1820f0dac59bb778b134d7f7
+    revision: 57c0884166dd0f1b7c484633b437fe11d5d62c89
     version: null
     source:
       Git: https://github.com/pulp-platform/Insitu-Cache.git

Bender.yml

@@ -29,12 +29,16 @@ sources:
   - hardware/src/tcdm_cache_interco.sv
   - hardware/src/tcdm_id_remapper.sv
   - hardware/src/spatz_cache_amo.sv
+  - hardware/src/cachepool_tile_barrier.sv
+  - hardware/src/cachepool_cluster_barrier.sv
   # Level 1
   - hardware/src/cachepool_pkg.sv
   - hardware/src/cachepool_cc.sv
   # Level 2
   - hardware/src/cachepool_tile.sv
   # Level 3
+  - hardware/src/cachepool_group.sv
+
   - hardware/src/cachepool_cluster.sv
   # Level 4
   - hardware/tb/cachepool_cluster_wrapper.sv

Makefile

@@ -182,6 +182,7 @@ VLOG_DEFS = -DCACHEPOOL
 
 # Cluster configuration
 VLOG_DEFS += -DNUM_TILES=$(num_tiles)
+VLOG_DEFS += -DNumRemotePortTile=$(num_remote_ports_per_tile)
 VLOG_DEFS += -DNUM_CORES=$(num_cores)
 VLOG_DEFS += -DDATA_WIDTH=$(data_width)
 VLOG_DEFS += -DADDR_WIDTH=$(addr_width)
@@ -274,6 +275,7 @@ vsim: dpi ${SIMBIN_DIR}/cachepool_cluster.vsim
 
 .PHONY: clean
 clean: clean.sw clean.vsim
+	rm -rf $(HJSON_OUT)
 
 ########
 # Lint #

config/cachepool.hjson

@@ -12,7 +12,7 @@
     data_width: 32,
     id_width_in: 6,                        // fixed for now
     id_width_out: 2,                       // fixed for now
-    user_width: 17,
+    user_width: 18,
     axi_cdc_enable: false,
     sw_rst_enable: true,
     axi_isolate_enable: false,
@@ -29,9 +29,9 @@
 
     // Spatz parameters
     vlen: 512,
-    n_fpu: 0,
+    n_fpu: 4,
     n_ipu: 4,
-    spatz_fpu: false,
+    spatz_fpu: true,
     norvd: true,
 
     // Timing parameters (fixed defaults; tweak in template if needed)

config/cachepool_512.mk

@@ -48,11 +48,11 @@ l1d_coal_window ?= 2
 # L1 data cache number of ways per
 l1d_num_way ?= 4
 
-# L1 data cache size per tile (KiB)
+# L1 data cache size **per tile** (KiB)
 l1d_tile_size ?= 256
 
 # L1 data cache tag width (TODO: should be calcualted)
-l1d_tag_data_width ?= 52
+l1d_tag_data_width ?= 92
 
 ####################
 ##  CachePool CC  ##

config/cachepool_fpu_128.mk

@@ -43,7 +43,7 @@ l1d_size ?= 256
 l1d_bank_factor ?= 1
 
 # L1 coalecsing window
-l1d_coal_window ?= 2
+l1d_coal_window ?= 1
 
 # L1 data cache number of ways per
 l1d_num_way ?= 4

config/cachepool_fpu_512.mk

@@ -20,6 +20,8 @@ data_width ?= 32
 # Core addrwidth
 addr_width ?= 32
 
+num_remote_ports_per_tile ?= 1
+
 
 ######################
 ##  CachePool Tile  ##
@@ -52,7 +54,7 @@ l1d_num_way ?= 4
 l1d_tile_size ?= 256
 
 # L1 data cache tag width (TODO: should be calcualted)
-l1d_tag_data_width ?= 52
+l1d_tag_data_width ?= 92
 
 ####################
 ##  CachePool CC  ##

config/config.mk

@@ -29,6 +29,8 @@ include $(CACHEPOOL_DIR)/config/$(config).mk
 # Number of tiles
 num_tiles ?= 1
 
+num_remote_ports_per_tile ?= 1
+
 # Number of cores
 num_cores ?= 4
 
@@ -109,11 +111,11 @@ ifneq ($(filter $(l1d_cacheline_width),128 256 512),$(l1d_cacheline_width))
 endif
 
 ifeq ($(l1d_cacheline_width),512)
-  axi_user_width := 17
+  axi_user_width := 18
 else ifeq ($(l1d_cacheline_width),256)
   axi_user_width := 19
 else ifeq ($(l1d_cacheline_width),128)
-  axi_user_width := 21
+  axi_user_width := 22
 endif
 
 #####################

hardware/src/cachepool_cc.sv

@@ -55,8 +55,8 @@ module cachepool_cc
     parameter type                                         acc_issue_req_t          = logic,
     parameter type                                         acc_issue_rsp_t          = logic,
     parameter type                                         acc_rsp_t                = logic,
-    parameter type                                         dma_events_t             = logic,
-    parameter type                                         dma_perf_t               = logic,
+    // parameter type                                         dma_events_t             = logic,
+    // parameter type                                         dma_perf_t               = logic,
     /// FPU configuration.
     parameter fpu_implementation_t                         FPUImplementation        = fpu_implementation_t'(0),
     /// Boot address of core.