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Example SystemVerilog output from SilverOak stage 1#951
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blaxill wants to merge 1 commit intoproject-oak:mainfrom
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Example SystemVerilog output from SilverOak stage 1#951blaxill wants to merge 1 commit intoproject-oak:mainfrom
blaxill wants to merge 1 commit intoproject-oak:mainfrom
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Not intended to be merged, just to show generated SystemVerilog