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Computer Organization

Project Phase-2

RISC-V Simulator

Pipelining

SURYAVARMAN E-CS20B057

PRATHIK KULKARNI-CS20B056

Abstract:

RISC-V is an open standard instruction set architecture (ISA) that began in 2010 and is based on established reduced instruction set computer (RISC) principles. Unlike most other ISA designs, RISC-V is provided under open source licenses that do not require fees to use. A number of companies are offering or have announced RISC-V hardware, open-source operating systems with RISC-V support are available, and the instruction set is supported in several popular software toolchains.

Synopsis:

We try to simulate the operations of RISC-V using a simulator built using javascript. Each line of the code was taken as an input in the form of a string and then stored in an array. Then each of the lines was processed separately using the code written in javascript with the help of functions and if-else statement(s). We then hoisted the website using Github.

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