devices: add flash-nandfctrl2 driver by lukileczo · Pull Request #421 · phoenix-rtos/plo

lukileczo · 2026-03-17T12:27:10Z

YT: CSAT-158

Description

Motivation and Context

Types of changes

Bug fix (non-breaking change which fixes an issue)
New feature (non-breaking change which adds functionality)
Breaking change (fix or feature that would cause existing functionality to change)
Chore (refactoring, style fixes, git/CI config, submodule management, no code logic changes)

How Has This Been Tested?

Already covered by automatic testing.
New test added: (add PR link here).
Tested by hand on: riscv64-gr765-vcu118

Checklist:

My change requires a change to the documentation.
I have updated the documentation accordingly.
I have added tests to cover my changes.
All new and existing linter checks and tests passed.
My changes generate no new compilation warnings for any of the targets.

Special treatment

This PR needs additional PRs to work (list the PRs, preferably in merge-order).
I will merge this PR by myself when appropriate.

gemini-code-assist · 2026-03-17T12:27:32Z

Summary of Changes

Hello, I'm Gemini Code Assist¹! I'm currently reviewing this pull request and will post my feedback shortly. In the meantime, here's a summary to help you and other reviewers quickly get up to speed!

This pull request delivers a crucial new component: a GRLIB NAND Flash Controller 2 driver. This driver significantly expands the system's storage capabilities by enabling robust and compliant interaction with NAND flash devices. It handles low-level flash operations, bad block management, and adapts to various flash configurations through ONFI 4.0 parameter parsing, ensuring reliable data storage and retrieval for embedded systems.

Highlights

New NAND Flash Controller Driver: Introduced a new driver for the GRLIB NAND Flash Controller 2 (NANDFCTRL2), enabling interaction with NAND flash memory.
ONFI 4.0 Support: Implemented support for ONFI 4.0 specifications, allowing the driver to dynamically detect and configure flash parameters and timings.
Data and Metadata Interfaces: Provided separate interfaces for data (read, write, erase) and metadata (spare area) operations, including block caching and bad block management.
Build System and Linker Script Updates: Integrated the new driver into the build system and adjusted linker scripts to accommodate the increased memory footprint.

Changelog

devices/flash-nandfctrl2/Makefile
- Added Makefile for the new flash-nandfctrl2 driver.
devices/flash-nandfctrl2/data.c
- Implemented the data interface for NAND flash, including read, write, erase, and sync operations.
- Incorporated block caching and bad block handling logic.
devices/flash-nandfctrl2/data.h
- Defined the data interface for the NAND flash controller.
devices/flash-nandfctrl2/meta.c
- Implemented the metadata interface for NAND flash, providing read and write access to spare areas.
devices/flash-nandfctrl2/nandfctrl2.c
- Implemented the core GRLIB NANDFCTRL2 flash driver, managing register access and command execution.
- Integrated ONFI parameter parsing and timing configuration.
- Added bad block scanning and marking functionalities.
devices/flash-nandfctrl2/nandfctrl2.h
- Defined structures and public API for the NANDFCTRL2 driver.
devices/flash-nandfctrl2/onfi-4.c
- Implemented ONFI 4.0 parameter page deserialization and timing mode retrieval functions.
devices/flash-nandfctrl2/onfi-4.h
- Defined ONFI 4.0 data structures and related constants.
hal/riscv64/gaisler/gr765/Makefile
- Updated the Makefile to include the new flash-nandfctrl2 device in PLO_ALLDEVICES.
ld/riscv64-gr765.ldt
- Increased SIZE_PLO from 0x40000 to 0x1000000 to accommodate the new driver.
riscv-sbi/ld/gr765.ldt
- Increased SIZE_PAYLOAD from 0x40000 to 0x1000000 to accommodate the new driver.

Activity

The pull request introduces a new feature.
The changes have been manually tested on riscv64-gr765-vcu118.

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Code Review

This pull request introduces a new GRLIB NANDFCTRL2 flash driver, including data and metadata interfaces, and integrates it into the build system and linker scripts. The changes enable support for NAND flash memory, providing functionalities for reading, writing, erasing, and managing bad blocks. The implementation includes ONFI 4.0 parameter page parsing and timing configuration. Several areas require attention regarding clarity, hardware register documentation, and adherence to configuration best practices for device-specific parameters. Additionally, a critical compilation error was identified in the header file for an undefined struct, and significant memory allocation changes in linker scripts require justification.

devices/flash-nandfctrl2/nandfctrl2.c

devices/flash-nandfctrl2/nandfctrl2.h

gemini-code-assist · 2026-03-17T12:30:28Z

devices/flash-nandfctrl2/meta.c

+
+	totalSparesz = (nand->info.size / nand->info.writesz) * nand->info.spareavail;
+
+	if ((offs >= nand->info.size) || (len > totalSparesz) || ((offs % nand->info.writesz) != 0U)) {


The validation (offs % nand->info.writesz) != 0U implies that offs must be page-aligned. However, the meta_read and meta_write functions are intended to operate on the spare area (metadata). If offs represents an offset within the logical address space of the metadata device, it should be aligned to nand->info.spareavail or some other metadata-specific unit, not nand->info.writesz (which is the data page size). This logic is ambiguous and could lead to incorrect behavior or unexpected validation failures. Please clarify the intended meaning of offs for the metadata device and adjust the validation accordingly.

devices/flash-nandfctrl2/data.c

devices/flash-nandfctrl2/nandfctrl2.c

gemini-code-assist · 2026-03-17T12:30:28Z

ld/riscv64-gr765.ldt


 #define ADDR_DDR 0x10000
-#define SIZE_PLO 0x40000
+#define SIZE_PLO 0x1000000


The SIZE_PLO has been significantly increased from 0x40000 to 0x1000000. This is a substantial change in memory allocation for the loader. While it might be necessary for the new NAND driver, such a large increase should be explicitly justified in the pull request description to ensure efficient memory usage and avoid unnecessary resource consumption.

gemini-code-assist · 2026-03-17T12:30:28Z

riscv-sbi/ld/gr765.ldt


 #define ADDR_DDR 0x00000
 #define SIZE_SBI 0x10000
+#define SIZE_PAYLOAD 0x1000000


The SIZE_PAYLOAD has been significantly increased from 0x40000 to 0x1000000. Similar to SIZE_PLO, this is a substantial change in memory allocation for the payload. Please provide justification for this large increase to ensure it's necessary and optimized.

github-actions · 2026-03-17T13:15:45Z

Unit Test Results

9 553 tests 8 961 ✅ 53m 27s ⏱️
591 suites 592 💤
1 files 0 ❌

Results for commit 07024fb.

YT: CSAT-158

lukileczo force-pushed the lukileczo/csat-158 branch from efc4cc0 to 2923ac3 Compare March 17, 2026 12:29

gemini-code-assist bot reviewed Mar 17, 2026

View reviewed changes

lukileczo force-pushed the lukileczo/csat-158 branch from 2923ac3 to 07024fb Compare March 17, 2026 12:57

devices: add flash-nandfctrl2 driver

ba9395d

YT: CSAT-158

lukileczo force-pushed the lukileczo/csat-158 branch from 07024fb to ba9395d Compare March 17, 2026 15:48

lukileczo marked this pull request as draft March 20, 2026 16:21

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devices: add flash-nandfctrl2 driver#421

devices: add flash-nandfctrl2 driver#421
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		totalSparesz = (nand->info.size / nand->info.writesz) * nand->info.spareavail;

		if ((offs >= nand->info.size) \|\| (len > totalSparesz) \|\| ((offs % nand->info.writesz) != 0U)) {

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lukileczo commented Mar 17, 2026

Description

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