Hardware Interview Questions

Introduction

This project presents solutions to common hardware design/VLSI interview questions. Presented are SystemVerilog implementations alongside self-checking verification environments. Thorough discussion on the elements saught by interviewer in a candidates solution provided.

System Requirements

• cmake >= 3.2
• systemc >= 2.3.1
• verilator >= 3.9
• clang >= 3.9

Build Steps (SIM)

git clone https://github.com/stephenry/hw_interview_questions
cd hw_interview_questions
git submodule update --init --recursive
mkdir build
cd build
cmake ../
make

PD (VIVADO)

A standard Vivado flow is supported for each answer. PD libaries must be explicitly selected during configuration (below). Within each answer, a new target 'vivado' is present that invokes a standard Vivado flow.

cmake ../ -DTARGET_VIVADO
make vivado

Run Steps

Upon successful completion of the build process. Tests can be executed by invoking the generated executable in the RTL directory.

Answers

• count_ones Answer to compute the population count of an input vector.
• fifo_async Answer to demonstrate the construction of a standard asynchronous FIFO.
• fifo_n Answer to construct N-statically sized FIFO from a single dual-ported, synchronous SRAM.
• fifo_sr Answer to implement a shift-register FIFO in a power efficient manner.
• fifo_ptr Answer to implement a ptr-based FIFO.
• gates_from_MUX2X1 Answer to derive AND, OR, XOR and INV logic gates from a MUX2X standard cell.
• increment Answer to derive logic to compute an increment function.
• latency Answer to compute the average latency of a command stream to and from some external agent.
• multi_counter Answer to demonstrate basic forwarding and pipeline concepts. Multiple counters are retained in a central state table. They are then randomly incremented or decremented on demand.
• multi_counter_variant Alternate solutions to multi_counter problem.
• one_or_two Answer to detect whether for an arbitrary input vector, 0-bits are set, 1-bit is set, or greater than 1 bit is set.
• mcp_formulation (Multi-Cycle Path Formulation) Answer to pass a vector between two clock domains using a multi-cycle path.
• detect_sequence Answer to detect a given sequence within an input serial stream.
• vending_machine_fsm Answer to design a FSM to emulate the behavior of a simple vending machine.
• vending_machine_dp Variant of FSM solution whereby some accumulation of a running count is required before an IRN-BRU shall be emitted.
• clk_div_by_3 Divide a clock by an odd number while retaining a 50% duty cycle.
• missing_duplicated_word Answer to detect the value of a non-duplicated integer in a state table containing duplicated entries.
• multiply_by_21 Answer to demonstrate how a constant value can be efficiently multiplied against a randomized vector.

Disclaimer

Contributions are welcome however please consider that the current project remains very much a work in progress and that ancillary libraries, upon which this code depends, remain under active development.