[Intel-SIG] 5.15-ClearWater PMU support for core#82

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quanxianwang wants to merge 29 commits intoopenvelinux:5.15-velinuxfrom

quanxianwang:PMU-velinux-kernel-5.15-legacy-core

Commits on Oct 10, 2025

KVM: x86: Advertise AVX-VNNI-INT8 CPUID to user space

Jiaxi Chen
authored and
quanxianwang
committed
x86/cpu: Add model number for Intel Clearwater Forest processor

aegl
authored and
quanxianwang
committed
x86: KVM: Advertise CPUIDs for new instructions in Clearwater Forest

taosu-linux
authored and
quanxianwang
committed
x86/cpu: Add model number for another Intel Arrow Lake mobile processor

aegl
authored and
quanxianwang
committed
x86/cpu/vfm: Add/initialize x86_vfm field to struct cpuinfo_x86

aegl
authored and
quanxianwang
committed
x86/cpu/vfm: Add new macros to work with (vendor/family/model) values

aegl
authored and
quanxianwang
committed
x86/cpu/vfm: Update arch/x86/include/asm/intel-family.h

aegl
authored and
quanxianwang
committed
x86/cpu: Switch to new Intel CPU model defines

aegl
authored and
quanxianwang
committed
x86/cpu/intel: Switch to new Intel CPU model defines

aegl
authored and
quanxianwang
committed
x86/cpu/intel: Drop stray FAM6 check with new Intel CPU model defines

andyhhp
authored and
quanxianwang
committed
perf/x86/intel: Switch to new Intel CPU model defines

aegl
authored and
quanxianwang
committed

Commits on Oct 28, 2025

perf/x86/intel: Use the common uarch name for the shared functions

Kan Liang
authored and
quanxianwang
committed
perf/x86/intel: Factor out the initialization code for SPR

Kan Liang
authored and
quanxianwang
committed
perf/x86/intel: Factor out the initialization code for ADL e-core

Kan Liang
authored and
quanxianwang
committed
perf/x86/intel: Apply the common initialization code for ADL

Kan Liang
authored and
quanxianwang
committed
perf/x86/intel: Clean up the hybrid CPU type handling code

Kan Liang
authored and
quanxianwang
committed
perf/x86/intel: Add common intel_pmu_init_hybrid()

Kan Liang
authored and
quanxianwang
committed
perf/x86/intel: Fix broken fixed event constraints extension

Kan Liang
authored and
quanxianwang
committed
perf/x86/intel: Support the PEBS event mask

Kan Liang
authored and
quanxianwang
committed
perf/x86: Support counter mask

Kan Liang
authored and
quanxianwang
committed
perf/x86: Add Lunar Lake and Arrow Lake support

Kan Liang
authored and
quanxianwang
committed
perf/x86/intel: Rename model-specific pebs_latency_data functions

Kan Liang
authored and
quanxianwang
committed
perf/x86/intel: Support new data source for Lunar Lake

Kan Liang
authored and
quanxianwang
committed
perf/x86: Add config_mask to represent EVENTSEL bitmask

Kan Liang
authored and
quanxianwang
committed
perf/x86/intel: Support PERFEVTSEL extension

Kan Liang
authored and
quanxianwang
committed
perf/x86/intel: Support Perfmon MSRs aliasing

Kan Liang
authored and
quanxianwang
committed
perf/x86/intel: Add PMU support for Clearwater Forest

Dapeng Mi
authored and
quanxianwang
committed
perf/x86/intel: Parse CPUID archPerfmonExt leaves for non-hybrid CPUs

Dapeng Mi
authored and
quanxianwang
committed
perf/x86/intel: Introduce pairs of PEBS static calls

Dapeng Mi
authored and
quanxianwang
committed

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[Intel-SIG] 5.15-ClearWater PMU support for core#82

[Intel-SIG] 5.15-ClearWater PMU support for core#82
quanxianwang wants to merge 29 commits intoopenvelinux:5.15-velinuxfrom
quanxianwang:PMU-velinux-kernel-5.15-legacy-core

Commits on Oct 10, 2025

KVM: x86: Advertise AVX-VNNI-INT8 CPUID to user space

x86/cpu: Add model number for Intel Clearwater Forest processor

x86: KVM: Advertise CPUIDs for new instructions in Clearwater Forest

x86/cpu: Add model number for another Intel Arrow Lake mobile processor

x86/cpu/vfm: Add/initialize x86_vfm field to struct cpuinfo_x86

x86/cpu/vfm: Add new macros to work with (vendor/family/model) values

x86/cpu/vfm: Update arch/x86/include/asm/intel-family.h

x86/cpu: Switch to new Intel CPU model defines

x86/cpu/intel: Switch to new Intel CPU model defines

x86/cpu/intel: Drop stray FAM6 check with new Intel CPU model defines

perf/x86/intel: Switch to new Intel CPU model defines

Commits on Oct 28, 2025

perf/x86/intel: Use the common uarch name for the shared functions

perf/x86/intel: Factor out the initialization code for SPR

perf/x86/intel: Factor out the initialization code for ADL e-core

perf/x86/intel: Apply the common initialization code for ADL

perf/x86/intel: Clean up the hybrid CPU type handling code

perf/x86/intel: Add common intel_pmu_init_hybrid()

perf/x86/intel: Fix broken fixed event constraints extension

perf/x86/intel: Support the PEBS event mask

perf/x86: Support counter mask

perf/x86: Add Lunar Lake and Arrow Lake support

perf/x86/intel: Rename model-specific pebs_latency_data functions

perf/x86/intel: Support new data source for Lunar Lake

perf/x86: Add config_mask to represent EVENTSEL bitmask

perf/x86/intel: Support PERFEVTSEL extension

perf/x86/intel: Support Perfmon MSRs aliasing

perf/x86/intel: Add PMU support for Clearwater Forest

perf/x86/intel: Parse CPUID archPerfmonExt leaves for non-hybrid CPUs

perf/x86/intel: Introduce pairs of PEBS static calls