Skip to content

fix #300 #313

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
davideschiavone merged 2 commits into from
Feb 23, 2026
Merged

fix #300 #313

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
45f099d
fix #300
davideschiavone Feb 14, 2026
a4c5516
write to RF only during x-if result phase
davideschiavone Feb 18, 2026
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
2 changes: 0 additions & 2 deletions rtl/cve2_decoder.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -91,7 +91,6 @@ module cve2_decoder #(

// Core-V eXtension interface (CV-X-IF)
input cve2_pkg::readregflags_t x_issue_resp_register_read_i,
input cve2_pkg::writeregflags_t x_issue_resp_writeback_i,

// jump/branches
output logic jump_in_dec_o, // jump is being calculated in ALU
Expand Down Expand Up @@ -663,7 +662,6 @@ module cve2_decoder #(
if(XInterface) begin
rf_ren_a_o = x_issue_resp_register_read_i[0];
rf_ren_b_o = x_issue_resp_register_read_i[1];
rf_we = x_issue_resp_writeback_i;
rf_wdata_sel_o = $bits(rf_wdata_sel_o)'({RF_WD_COPROC});
end
end
Expand Down
15 changes: 10 additions & 5 deletions rtl/cve2_id_stage.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -284,10 +284,11 @@ module cve2_id_stage #(
end
end

logic coproc_done;

// CV-X-IF
if (XInterface) begin: gen_xif

logic coproc_done;
logic [X_INSTR_INFLIGHT-1:0] scoreboard_d, scoreboard_q;
id_t x_instr_id_d, x_instr_id_q;

Expand Down Expand Up @@ -342,8 +343,6 @@ module cve2_id_stage #(

assign multicycle_done = lsu_req_dec ? lsu_resp_valid_i : (illegal_insn_dec ? coproc_done : ex_valid_i);

assign coproc_done = (x_issue_valid_o & x_issue_ready_i & ~x_issue_resp_i.writeback) | (x_result_valid_i & x_result_i.we);

// Issue Interface
assign x_issue_valid_o = instr_executing & illegal_insn_dec & (id_fsm_q == FIRST_CYCLE) & scoreboard_free;
assign x_issue_req_o.instr = instr_rdata_i;
Expand Down Expand Up @@ -372,7 +371,9 @@ module cve2_id_stage #(
x_issue_resp_t unused_x_issue_resp;
logic unused_x_result_valid;
x_result_t unused_x_result;
logic unused_coproc_done;

assign unused_coproc_done = coproc_done;

assign multicycle_done = lsu_req_dec ? lsu_resp_valid_i : ex_valid_i;
assign scoreboard_busy = 1'b0;
Expand Down Expand Up @@ -561,7 +562,6 @@ module cve2_id_stage #(

// Core-V eXtension Interface (CV-X-IF)
.x_issue_resp_register_read_i(x_issue_resp_i.register_read),
.x_issue_resp_writeback_i(x_issue_resp_i.writeback),

// jump/branches
.jump_in_dec_o (jump_in_dec),
Expand Down Expand Up @@ -775,6 +775,7 @@ module cve2_id_stage #(
branch_set_raw_d = 1'b0;
jump_set_raw = 1'b0;
perf_branch_o = 1'b0;
coproc_done = 1'b1;

if (instr_executing_spec) begin
unique case (id_fsm_q)
Expand Down Expand Up @@ -827,6 +828,7 @@ module cve2_id_stage #(
if(x_issue_resp_i.accept && x_issue_resp_i.writeback) begin
id_fsm_d = MULTI_CYCLE;
stall_coproc = 1'b1;
coproc_done = 1'b0;
end
else begin
id_fsm_d = FIRST_CYCLE;
Expand All @@ -853,7 +855,10 @@ module cve2_id_stage #(
if(multdiv_en_dec) begin
rf_we_raw = rf_we_dec & ex_valid_i;
end

if (illegal_insn_dec && XInterface) begin
Copy link
Copy Markdown
Member

@MikeOpenHWGroup MikeOpenHWGroup Feb 16, 2026

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

This will work in simulation. Will synthesis produce the expected results?

Copy link
Copy Markdown
Author

@davideschiavone davideschiavone Feb 17, 2026

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

it should yes - but we should try with some real co-processor

Copy link
Copy Markdown
Member

@MikeOpenHWGroup MikeOpenHWGroup Feb 17, 2026

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I am not worried about the case when there is a module connected to the XIF and the parameter XInterface is set to 1. That will work as expected in both simulation and synthesis. What is less clear is what will be produced in synthesis when XInterface is 0.

Copy link
Copy Markdown
Author

@davideschiavone davideschiavone Feb 17, 2026

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

In that case, coproc_done will always be 1 as its default value is set here

and it could go to zero only if this statement is true.
This can never be as the XInterface parameter would be 0 at design time - so the synthesizer would simply remove this logic, and there should not be any latch inferred.

Similarly, as this if statement would always be 0 , the coproc_done value here would never be assigned, so it would keep its default value at 1 - if you prefer for readability, I can do else coproc_done = 1'b1 - that's why when XInterface is 0 the CPU is Sequentially Equivalent.

If instead you refer to the situation that there is an illegal instruction and you are in the MULTI_CYCLE state, then no worries, you can never be here as you would never been entered this state if illegals and XInterace is 0. That's why when XInterface is 0 the CPU is Sequentially Equivalent.

coproc_done = x_result_valid_i;
rf_we_raw = x_result_valid_i & x_result_i.we;
end
if (multicycle_done) begin
id_fsm_d = FIRST_CYCLE;
end else begin
Expand Down
Loading