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1. texerai/maveric2 texerai/maveric2 Public

   MAVERIC CORE 2.0 is a classical 5-stage pipelined RISC-V processor

   SystemVerilog 3

2. osoc_season1_nurman_olzhas osoc_season1_nurman_olzhas Public

   This repository contains design and verification files for a multicycle RISC-V processor designed as part of "One Student One Chip" program

   SystemVerilog

3. ysyx_201979054 ysyx_201979054 Public

   Verilog 1

4. osoc_season2_olzhas_nurman osoc_season2_olzhas_nurman Public

   This repository contains design and verification files for a 5-stage pipelined RISC-V processor

   SystemVerilog

5. conv_w_serial_mult conv_w_serial_mult Public

   This repository contains design files for hardware module for computing convolution operation on FPGA using serial multipliers.

   SystemVerilog

6. i2c_oled_driver i2c_oled_driver Public

   This repository contains design that realizes the logic for configuring SSD1306 OLED display. It uses I2C for writing data.

   Verilog