Added SCU35 dev board, but not sure how fusesoc handles PDI files

corescore.core

@@ -305,6 +305,14 @@ filesets:
       - data/libero-post-instructions.txt:
           { file_type: user, copyto: post-instructions.txt }
 
+  scu35:
+    files:
+      - rtl/corescore_scu35_clock_gen.v: { file_type: verilogSource }
+      - rtl/corescore_scu35.v: { file_type: verilogSource }
+      - data/vivado_waive.tcl: { file_type: tclSource }
+      - data/scu35.xdc: { file_type: xdc }
+
+
   sockit:
     files:
       - data/sockit.sdc: { file_type: SDC }
@@ -849,6 +857,14 @@ targets:
         <<: *liberoMPF300
         die: MPF300TS_ES
 
+  scu35:
+    default_tool: vivado
+    filesets: [base, emitter_serv, scu35]
+    generate: [corescorecore: {count: 83}]
+    tools:
+      vivado: { part: xcsu35p-sbvb625-2-e }
+    toplevel: corescore_scu35
+
   sim:
     default_tool: verilator
     description: Verilator testbench with 10 cores + SERV emitter

data/scu35.xdc

@@ -0,0 +1,14 @@
+set_property PACKAGE_PIN E23  [get_ports "SYSCLK_N"] ;
+set_property IOSTANDARD  LVDS [get_ports "SYSCLK_N"] ;
+set_property PACKAGE_PIN F23  [get_ports "SYSCLK_P"] ;
+set_property IOSTANDARD  LVDS [get_ports "SYSCLK_P"] ;
+
+create_clock -add -name sys_clk_pin -period 10 [get_nets i_clk];
+
+set_property PACKAGE_PIN AB18     [get_ports "led0_g"] ;
+set_property IOSTANDARD  LVCMOS33 [get_ports "led0_g"] ;
+
+set_property PACKAGE_PIN AB6     [get_ports "scu35_uartb_txd"] ;
+set_property IOSTANDARD  LVCMOS33 [get_ports "scu35_uartb_txd"] ;
+
+set_property RAM_STYLE block [get_cells corescorecore/core_*/serving/ram/mem_reg]

rtl/corescore_scu35.v

@@ -0,0 +1,51 @@
+`default_nettype none
+module corescore_scu35
+(
+ input wire  SYSCLK_P,
+ input wire  SYSCLK_N,
+ output wire led0_g,
+ output wire scu35_uartb_txd);
+
+   wire      i_clk;
+   wire      clk;
+   wire      rst;
+
+   //Mirror UART output to LED
+   assign led0_g = scu35_uartb_txd;
+
+   IBUFGDS ibufds(
+      .I (SYSCLK_P),
+      .IB(SYSCLK_N),
+      .O (i_clk));
+
+   corescore_scu35_clock_gen
+   clock_gen
+     (.i_clk (i_clk),
+      .o_clk (clk),
+      .o_rst (rst));
+
+   parameter memfile_emitter = "emitter.hex";
+
+   wire [7:0]  tdata;
+   wire        tlast;
+   wire        tvalid;
+   wire        tready;
+
+   corescorecore corescorecore
+     (.i_clk     (clk),
+      .i_rst     (rst),
+      .o_tdata   (tdata),
+      .o_tlast   (tlast),
+      .o_tvalid  (tvalid),
+      .i_tready  (tready));
+
+   emitter #(.memfile (memfile_emitter)) emitter
+     (.i_clk     (clk),
+      .i_rst     (rst),
+      .i_tdata   (tdata),
+      .i_tlast   (tlast),
+      .i_tvalid  (tvalid),
+      .o_tready  (tready),
+      .o_uart_tx (scu35_uartb_txd));
+
+endmodule

rtl/corescore_scu35_clock_gen.v

@@ -0,0 +1,44 @@
+`default_nettype none
+module corescore_scu35_clock_gen
+  (input wire  i_clk,
+   output wire o_clk,
+   output reg  o_rst);
+
+   wire   clkfb;
+   wire   locked;
+   reg 	  locked_r;
+
+   MMCME4_ADV
+     #(.DIVCLK_DIVIDE    (4),
+       .CLKFBOUT_MULT_F  (32.000),
+       .CLKOUT0_DIVIDE_F (50.0),
+       .CLKIN1_PERIOD    (10.0), //100MHz
+       .STARTUP_WAIT     ("FALSE"))
+   mmcm
+     (.CLKFBOUT    (clkfb),
+      .CLKFBOUTB   (),
+      .CLKOUT0     (o_clk),      // 16MHz
+      .CLKOUT0B    (),
+      .CLKOUT1     (),
+      .CLKOUT1B    (),
+      .CLKOUT2     (),
+      .CLKOUT2B    (),
+      .CLKOUT3     (),
+      .CLKOUT3B    (),
+      .CLKOUT4     (),
+      .CLKOUT5     (),
+      .CLKOUT6     (),
+      .CLKIN1      (i_clk),
+      .CLKIN2      (1'b0),
+      .CLKINSEL    (1'b1),
+      .LOCKED      (locked),
+      .PWRDWN      (1'b0),
+      .RST         (1'b0),
+      .CLKFBIN     (clkfb));
+
+   always @(posedge o_clk) begin
+      locked_r <= locked;
+      o_rst  <= !locked_r;
+   end
+
+endmodule