add support for de10_nano with mistral toolchain

corescore.core

@@ -132,7 +132,13 @@ filesets:
       - data/de10_nano.tcl: { file_type: tclSource }
       - rtl/de0_nano_clock_gen.v: { file_type: verilogSource }
       - rtl/corescore_de10_nano.v: { file_type: verilogSource }
-
+
+  de10_nano_mistral:
+    files:
+      - data/de10_nano_mistral.qsf : {file_type: QSF}
+      - rtl/corescore_emitter_uart.v: { file_type: verilogSource }
+      - rtl/corescore_de10_nano_mistral.v: { file_type: verilogSource } 
+
   de5_net:
     files:
       - data/de5_net.sdc: { file_type: SDC }
@@ -498,6 +504,17 @@ targets:
         board_device_index : 2
     toplevel: corescore_de10_nano
 
+  de10_nano_mistral:
+    default_tool: mistral
+    filesets: [rtl, de10_nano_mistral]
+    generate: [corescorecore_de10_nano_mistral]
+    tools:
+      mistral:
+        yosys_synth_options : [-family cyclonev -nodsp ]
+        nextpnr_options: [--freq,12.5]
+        device: 5CSEBA6U23I7
+    toplevel: corescore_de10_nano_mistral
+
   de5_net:
     default_tool: quartus
     filesets: [rtl, de5_net]
@@ -851,11 +868,17 @@ generate:
     generator: corescorecore
     parameters:
       count: 61
+
 
   corescorecore_de10_nano:
     generator: corescorecore
     parameters:
       count: 271
+
+  corescorecore_de10_nano_mistral:
+    generator: corescorecore
+    parameters:
+      count: 84
 
   corescorecore_de5_net:
     generator: corescorecore

data/de10_nano_mistral.qsf

@@ -0,0 +1,12 @@
+set_location_assignment PIN_V11 -to i_clk
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to i_clk
+
+
+# GPIO0 Pin 1
+set_location_assignment PIN_Y15 -to o_uart_tx
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to uart_txd
+
+#KEY[0]
+set_location_assignment PIN_AH17 -to i_rst_n
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to i_rst_n
+

rtl/corescore_de10_nano_mistral.v

@@ -0,0 +1,49 @@
+
+module corescore_de10_nano_mistral
+  (
+   input  wire     i_clk,
+   input wire i_rst_n,
+   output wire o_uart_tx);
+
+
+   reg  div_clk = 0;
+   reg  counter = 0;
+
+
+   always@(posedge i_clk) begin
+
+      counter <= counter + 1;
+      if(counter == 1) div_clk <= ~div_clk;
+
+   end   
+
+
+   wire	       rst;
+
+   assign rst  = !i_rst_n;
+
+   parameter memfile_emitter = "emitter.hex";
+
+   wire [7:0]  tdata;
+   wire        tlast;
+   wire        tvalid;
+   wire        tready;
+
+   corescorecore corescorecore
+     (.i_clk     (div_clk),
+      .i_rst     (rst),
+      .o_tdata   (tdata),
+      .o_tlast   (tlast),
+      .o_tvalid  (tvalid),
+      .i_tready  (tready));
+
+   corescore_emitter_uart #(.clk_freq_hz (12_500_000)) emitter
+     (.i_clk     (div_clk),
+      .i_rst     (rst),
+      .i_data    (tdata),
+      .i_valid   (tvalid),
+      .o_ready   (tready),
+      .o_uart_tx (o_uart_tx));
+
+endmodule
+