verilog-examples

test code for anyone learning the language verilog

Name		Name	Last commit message	Last commit date
Latest commit History 2 Commits
README.md		README.md
alu.v		alu.v
alu_tb.v		alu_tb.v
and2.v		and2.v
and2_tb.v		and2_tb.v
dec3to8.v		dec3to8.v
dec3to8_tb.v		dec3to8_tb.v
dff.v		dff.v
dff_tb.v		dff_tb.v
full_adder.v		full_adder.v
full_adder_tb.v		full_adder_tb.v
hello.v		hello.v

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