Dump of input ports with sub-range assignment contains complete parent vector #1365
Description
When assigning a single bit or multibit slice from a longer vector to an input port of an instance, nvc writes the whole vector from the parent scope to the dump file. VCD and FST are both affected. The issue only happens for input ports, output ports work as expected. The actual simulation works fine, i.e. internal signals of those instances s_bit and s_nibble contain the correct bit(slice) of the parent vector, and only the dump
FST file in Surfer:
FST file in GTKWave:
nvc version: nvc 1.19-devel (1.18.0.r76.g7d986433b) (Using LLVM 14.0.0)
Example VHDL code to replicate the issue:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity input_bug_single_bit is
port
(
i_single : in std_logic;
o_single : out std_logic
);
end entity;
architecture beh of input_bug_single_bit is
signal s_bit : std_logic;
begin
s_bit <= i_single;
o_single <= s_bit;
end architecture;
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity input_bug_multi_bit is
port
(
i_multi : in std_logic_vector(3 downto 0);
o_multi : out std_logic_vector(3 downto 0)
);
end entity;
architecture beh of input_bug_multi_bit is
signal s_nibble : std_logic_vector(3 downto 0);
begin
s_nibble <= i_multi;
o_multi <= s_nibble;
end architecture;
---------------------------------------------------------------------------
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity tb_slv_input_bug is
end entity;
architecture beh of tb_slv_input_bug is
signal s_vec_in : std_logic_vector(7 downto 0);
signal s_vec_out : std_logic_vector(7 downto 0);
begin
i_inst_single : entity work.input_bug_single_bit(beh)
port map (
i_single => s_vec_in(0), -- Dump of i_single is 8 bit wide despite being declared as a single bit!
o_single => s_vec_out(0)
);
i_inst_multi : entity work.input_bug_multi_bit(beh)
port map (
i_multi => s_vec_in(7 downto 4), -- Dump of i_multi is 8 bit wide despite being declared as 4 bit!
o_multi => s_vec_out(7 downto 4)
);
s_vec_out(3 downto 1) <= (others => '0');
p_seq : process
begin
s_vec_in <= x"00";
wait for 10 ns;
s_vec_in <= x"5f";
wait for 10 ns;
s_vec_in <= x"01";
wait for 10 ns;
s_vec_in <= x"aa";
wait for 10 ns;
wait;
end process;
end architecture;