Wrong signal in FST file #1340
Description
When I compile the following VHDL code (nvc 1.19-devel (1.18.0.r66.g3a60d57b6) (Using LLVM 21.1.4):
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY submodule IS
PORT (
i_clock : IN std_logic_vector(0 DOWNTO 0) := (OTHERS => '0');
i_counter_msb : IN std_logic_vector(0 DOWNTO 0) := (OTHERS => '0');
o_valid : OUT std_logic_vector(0 DOWNTO 0)
);
END ENTITY submodule;
ARCHITECTURE rtl OF submodule IS
SIGNAL r_valid : std_logic_vector(0 DOWNTO 0) := (OTHERS => '0');
BEGIN
o_valid <= r_valid;
proc_domain_clock : PROCESS (i_clock) IS
BEGIN
IF rising_edge(i_clock(0)) THEN
r_valid <= i_counter_msb;
END IF;
END PROCESS proc_domain_clock;
END ARCHITECTURE rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY issue IS
PORT (
i_clock : IN std_logic_vector(0 DOWNTO 0) := (OTHERS => '0');
o_counter : OUT std_logic_vector(7 DOWNTO 0);
o_valid : OUT std_logic_vector(0 DOWNTO 0)
);
END ENTITY issue;
ARCHITECTURE rtl OF issue IS
SIGNAL r_counter : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_submodule_valid : std_logic_vector(0 DOWNTO 0);
BEGIN
o_counter <= r_counter;
o_valid <= s_submodule_valid;
inst_submodule : ENTITY work.submodule
PORT MAP (
i_clock => i_clock,
i_counter_msb => r_counter(7 + 1 - 1 DOWNTO 7),
o_valid => s_submodule_valid
);
proc_domain_clock : PROCESS (i_clock) IS
BEGIN
IF rising_edge(i_clock(0)) THEN
r_counter <= r_counter + "00000001";
END IF;
END PROCESS proc_domain_clock;
END ARCHITECTURE rtl;I would assume that the signal ì_counter_msb in the FST file is of the type std_logic_vector(0 DOWNTO 0). However, the signal ì_counter_msb in the FST file is the original signal r_counter:
