Cores is a library of somewhat reusable hardware modules that I have
accumulated from different FPGA projects.


Installation
============

Create a new project with Xilinx ISE and all all files under rtl/ and tb/.
Optional: add the ISIM *.wcfg files under isim/. Now you can simulate any
module with ISIM or synthesize with XST, all from ISE.


Directory Structure
===================

doc/        Documentation
isim/       Scripts for running the Xilinx ISIM simulator
rtl/        Verilog and VHDL source files for synthesis
tb/         Testbench source files for verification