Fix MMC3 mapper IRQ timing with proper A12 toggle detection #2
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Problem
The MMC3 mapper implementation had incorrect IRQ timing that could cause issues with games relying on precise interrupt timing. The original implementation used a simplified scanline-based approach that triggered IRQs once per scanline at cycle 260, but this doesn't match the actual MMC3 hardware behavior.
Root Cause
The MMC3 mapper's IRQ counter should be decremented on A12 address line toggles during CHR ROM reads, not on a fixed scanline schedule. The A12 line (bit 12 of the PPU address bus) toggles when the PPU switches between different pattern table regions during background tile fetching.
Solution
This PR implements proper A12 toggle detection for accurate MMC3 IRQ timing:
Key Changes
last_a12field to the PPU to track the A12 address line stateread_chr()to detect A12 rising edge transitions (0→1) and trigger the mapper's IRQ logicstep_scanline()at cycle 260Before vs After
Testing
Added comprehensive tests covering:
Impact
This fix should resolve timing issues with MMC3 games that rely on precise interrupt timing for effects like:
The changes are minimal and maintain backward compatibility while significantly improving accuracy to match real MMC3 hardware behavior.
Verification
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