memory.sv

`include "memory_params.vh"

module memory
  #(
    parameter WORDS     = MEM_NUM_WORDS,
    parameter BITS      = MEM_NUM_BITS,
    parameter BASE_ADDR = MEM_BASE_ADDR,
    parameter ADDR_LEFT = $clog2(WORDS)-1
  )
  (
    output logic [BITS-1:0]  rdata,
    input                    clk,
    input  [BITS-1:0]        wdata,
    input                    rw_,
    input  [31:0]            addr,
    input  [3:0]             byte_en
  );

  // memory array
  logic [BITS-1:0] mem[0:WORDS-1];

  // Simple address logic - just use lower address bits  
  logic [ADDR_LEFT:0] local_addr;
  assign local_addr = addr[ADDR_LEFT:0];

  // Asynchronous read - always provide read data
  assign rdata = mem[local_addr];

  // Synchronous write logic
  always @(posedge clk) begin
    if (!rw_) begin
      case (byte_en)
        4'b0001: mem[local_addr][7:0]   <= wdata[7:0];
        4'b0011: mem[local_addr][15:0]  <= wdata[15:0];
        4'b1111: mem[local_addr]        <= wdata;
        default: ; // Do nothing for other patterns
      endcase
    end
  end

endmodule