equality.sv

module equality
 #(
    parameter NUM_BITS=32
 )

 (
    output logic                equal,
    output logic                not_equal,

    input logic [NUM_BITS-1:0]  data1,
    input logic [NUM_BITS-1:0]  data2,
    
    // Branch forwarding inputs
    input logic                 b_r1_fwd_s4,
    input logic                 b_r2_fwd_s4,
    input logic                 b_r1_fwd_s5,
    input logic                 b_r2_fwd_s5,
    input logic [NUM_BITS-1:0]  alu_out_s4,
    input logic [NUM_BITS-1:0]  reg_wdata
 );

 // Select forwarded values for comparison
 logic [NUM_BITS-1:0] r1_compare;
 logic [NUM_BITS-1:0] r2_compare;
 
 // Forward r1 with priority: Stage 4 > Stage 5 > Register file
 assign r1_compare = b_r1_fwd_s4 ? alu_out_s4 :
                     b_r1_fwd_s5 ? reg_wdata :
                     data1;
 
 // Forward r2 with priority: Stage 4 > Stage 5 > Register file
 assign r2_compare = b_r2_fwd_s4 ? alu_out_s4 :
                     b_r2_fwd_s5 ? reg_wdata :
                     data2;

 // Compare the forwarded values
 assign equal       = (r1_compare == r2_compare);
 assign not_equal   = ~equal;

endmodule