Complete the WDC 65C02 instruction set implementation

[mre]

This commit finishes implementing the standard Western Design Center 65C02 instruction set by adding the last missing instructions.

The main additions are the two low-power instructions WAI (Wait for Interrupt) and STP (Stop Processor), which allow the CPU to enter power-saving modes. I also added support for the BIT instruction with indexed addressing modes (zero page indexed and absolute indexed), and the indexed indirect jump instruction JMP (abs,X).

Additionally, the Cmos6502 variant now has better documentation that aims to explain all the improvements over the original NMOS 6502.

This closes issue #120.

[omarandlorraine]

It seems like the WAI and STP instructions stop the CPU until either any interrupt or a reset.

So then maybe instead of a boolean "halted" it would be better to have an enum "waiting_for", with the variants "Nothing", "Interrupt" and "Reset". The interrupt (when eventually implemented) and the reset could then set it to "Nothing", a condition checked in the "single_step" method.

Does that idea have legs?

[mre]

That's a brilliant idea @omarandlorraine. Let me change that. I would like to do this as part of #122, though, as it seems like a better fit for a follow-up PR to reduce the scope a bit. Do you agree?

[omarandlorraine]

Also, the "single_step" method could return a boolean: did I step over an instruction or not?

[mre]

I like that.

[mre]

Changed it such that single_step() returns a boolean. Thanks for the suggestion.

[mre]

I will go ahead and merge this as it sounds like the changes are only additive in nature and fill in the missing instructions for CMOS. If bugs remain, we can always fix them later, but the tests should give us a good baseline for future work.