GitHub - mpardalos/Vera: Verified Verilog Equivalence checker, written and verified in Coq.

Name		Name	Last commit message	Last commit date
Latest commit History 378 Commits
.claude		.claude
bin		bin
examples		examples
test		test
vera		vera
.envrc		.envrc
.gitignore		.gitignore
.gitmodules		.gitmodules
.ocamlformat		.ocamlformat
_CoqProject		_CoqProject
dune-project		dune-project
dune-workspace		dune-workspace
flake.lock		flake.lock
flake.nix		flake.nix
test.sh		test.sh
test_results_2025-01-14.txt		test_results_2025-01-14.txt
test_results_2025-01-15.txt		test_results_2025-01-15.txt
vera.opam		vera.opam