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uvm_axi
uvm_axi PublicForked from smartfoxdata/uvm_axi
uvm_axi is a uvm package for modeling and verifying AXI protocol
SystemVerilog 1
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uvm-1.2
uvm-1.2 PublicForked from beeflobill/uvm-1.2
A copy of the release from: http://www.accellera.org/images/downloads/standards/uvm/uvm-1.2.tar.gz. It's nice to browse code online.
SystemVerilog
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ibex
ibex PublicForked from lowRISC/ibex
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
SystemVerilog
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