Farrow Resampler (MATLAB + VHDL)

This repository provides Farrow-structure fractional resampling reference models in MATLAB and an FPGA-oriented VHDL linear resampler (with testbench).

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Repository Layout

.
├── Matlab/
│   ├── linear/     # 1st-order (2-tap) Farrow / linear interpolation resampler
│   ├── quad/       # 2nd-order Farrow resampler (quadratic)
│   └── cubic/      # 3rd-order Farrow resampler (cubic)
│
└── VHDL/
    ├── linear/     # Linear Farrow resampler core (hardware: linear only)
    └── TB/         # Testbench (I/Q stimulus + simulation helpers)

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MATLAB Folder

Matlab/ contains floating-point reference models used for verification and golden output generation:

• Linear: 1st-order Farrow (2 taps)
• Quadratic: 2nd-order Farrow
• Cubic: 3rd-order Farrow (cubic)

Use these models to:

• validate resampling behavior (upsampling and downsampling)
• compare interpolation orders
• generate reference outputs for VHDL simulation checks

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VHDL Folder

VHDL/ contains an FPGA-friendly linear resampler core and a testbench.

VHDL Linear Resampler Core

• Interpolation: linear (2-tap)
• Rate change: (0 : 2) (fractional rate changer)
  • Example valid rates: 0.001 to 1.999
• Implementation concept: phase accumulator + 2-tap interpolation (Farrow linear)

Only the linear resampler is implemented in VHDL in this repository.

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Testbench (TB) — I/Q Input Format

The testbench in VHDL/TB/ accepts complex data as I/Q samples stored line-by-line in a text file.

Required File Format (Important)

Each complex sample is written as two lines:

I0
Q0
I1
Q1
I2
Q2
...

So the first line is I0, the second line is Q0, the third line is I1, the fourth line is Q1, and so on.

Example Stimulus File

1024
-512
980
-490
900
-450
...

Interpretation:

• Sample 0: I=1024, Q=-512
• Sample 1: I=980, Q=-490
• Sample 2: I=900, Q=-450

Notes

• Values can be integers or fixed-point formatted numbers depending on how your TB is written.
• Ensure the TB and DUT agree on bit width, signed/unsigned, and scaling.

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Recommended Verification Flow

1. Generate reference outputs in MATLAB
   • Use Matlab/linear to create a golden output for the same input sequence.
2. Run VHDL simulation
   • Place the stimulus file in the expected TB location.
   • Simulate VHDL/TB to drive the DUT with the I/Q stream.
3. Compare results
   • Compare VHDL output against MATLAB linear reference output.

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Practical Notes

• For downsampling, an anti-aliasing lowpass filter is typically required before resampling (not included here).
• MATLAB models are intended as algorithm references; VHDL focuses on FPGA feasibility and streaming operation.

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License

Add your license information here (MIT / BSD / proprietary / etc.).