phy/generic_ddr: Change DDRLiteSPIClkGen's polarity to simplify LiteS…

[enjoy-digital]

…PIDDRPHYCore's code.

[danc86]

I tested this PR in my project, which is using Crosslink-NX with a Gigadevice GD25LQ128D flash chip. My design is working well with current Litespi master branch in DDR mode but it breaks with this patch applied.

Tomorrow I will try and collect some before and after traces so that we can compare what might be going wrong.

One thing to note is that my design requires extra_latency=1 to make DDR mode work. I wonder if this refactoring has changed the clock alignment such that this no longer lines up as it did before. I guess the Gigadevice is somehow more sensitive to clock signal alignment than other flash chips but I'm not sure how exactly. A trace will hopefully help to clarify.

[enjoy-digital]

Thanks @danc86 for the feedback. I'll try to do more testing on this.