Skip to content

[PW_SID:1069686] [v4] reset: spacemit: k3: Decouple composite reset lines #1648

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Closed
linux-riscv-bot wants to merge 1 commit into from
Closed

[PW_SID:1069686] [v4] reset: spacemit: k3: Decouple composite reset lines #1648

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
60 changes: 36 additions & 24 deletions drivers/reset/spacemit/reset-spacemit-k3.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -112,16 +112,21 @@ static const struct ccu_reset_data k3_apmu_resets[] = {
[RESET_APMU_SDH0] = RESET_DATA(APMU_SDH0_CLK_RES_CTRL, 0, BIT(1)),
[RESET_APMU_SDH1] = RESET_DATA(APMU_SDH1_CLK_RES_CTRL, 0, BIT(1)),
[RESET_APMU_SDH2] = RESET_DATA(APMU_SDH2_CLK_RES_CTRL, 0, BIT(1)),
[RESET_APMU_USB2] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0,
BIT(1)|BIT(2)|BIT(3)),
[RESET_APMU_USB3_PORTA] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0,
BIT(5)|BIT(6)|BIT(7)),
[RESET_APMU_USB3_PORTB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0,
BIT(9)|BIT(10)|BIT(11)),
[RESET_APMU_USB3_PORTC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0,
BIT(13)|BIT(14)|BIT(15)),
[RESET_APMU_USB3_PORTD] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0,
BIT(17)|BIT(18)|BIT(19)),
[RESET_APMU_USB2_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(1)),
[RESET_APMU_USB2_VCC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(2)),
[RESET_APMU_USB2_PHY] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(3)),
[RESET_APMU_USB3_A_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(5)),
[RESET_APMU_USB3_A_VCC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(6)),
[RESET_APMU_USB3_A_PHY] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(7)),
[RESET_APMU_USB3_B_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(9)),
[RESET_APMU_USB3_B_VCC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(10)),
[RESET_APMU_USB3_B_PHY] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(11)),
[RESET_APMU_USB3_C_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(13)),
[RESET_APMU_USB3_C_VCC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(14)),
[RESET_APMU_USB3_C_PHY] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(15)),
[RESET_APMU_USB3_D_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(17)),
[RESET_APMU_USB3_D_VCC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(18)),
[RESET_APMU_USB3_D_PHY] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(19)),
[RESET_APMU_QSPI] = RESET_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(1)),
[RESET_APMU_QSPI_BUS] = RESET_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(0)),
[RESET_APMU_DMA] = RESET_DATA(APMU_DMA_CLK_RES_CTRL, 0, BIT(0)),
Expand Down Expand Up @@ -151,10 +156,12 @@ static const struct ccu_reset_data k3_apmu_resets[] = {
[RESET_APMU_CPU7_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(26), 0),
[RESET_APMU_C1_MPSUB_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(28), 0),
[RESET_APMU_MPSUB_DBG] = RESET_DATA(APMU_PMU_CC2_AP, BIT(29), 0),
[RESET_APMU_UCIE] = RESET_DATA(APMU_UCIE_CTRL,
BIT(1) | BIT(2) | BIT(3), 0),
[RESET_APMU_RCPU] = RESET_DATA(APMU_RCPU_CLK_RES_CTRL, 0,
BIT(3) | BIT(2) | BIT(0)),
[RESET_APMU_UCIE_IP] = RESET_DATA(APMU_UCIE_CTRL, BIT(1), 0),
[RESET_APMU_UCIE_HOT] = RESET_DATA(APMU_UCIE_CTRL, BIT(2), 0),
[RESET_APMU_UCIE_MON] = RESET_DATA(APMU_UCIE_CTRL, BIT(3), 0),
[RESET_APMU_RCPU_AUDIO_SYS] = RESET_DATA(APMU_RCPU_CLK_RES_CTRL, 0, BIT(0)),
[RESET_APMU_RCPU_MCU_CORE] = RESET_DATA(APMU_RCPU_CLK_RES_CTRL, 0, BIT(2)),
[RESET_APMU_RCPU_AUDIO_APMU] = RESET_DATA(APMU_RCPU_CLK_RES_CTRL, 0, BIT(3)),
[RESET_APMU_DSI4LN2_ESCCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL3, 0, BIT(3)),
[RESET_APMU_DSI4LN2_LCD_SW] = RESET_DATA(APMU_LCD_CLK_RES_CTRL3, 0, BIT(4)),
[RESET_APMU_DSI4LN2_LCD_MCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL4, 0, BIT(9)),
Expand All @@ -164,16 +171,21 @@ static const struct ccu_reset_data k3_apmu_resets[] = {
[RESET_APMU_UFS_ACLK] = RESET_DATA(APMU_UFS_CLK_RES_CTRL, 0, BIT(0)),
[RESET_APMU_EDP0] = RESET_DATA(APMU_LCD_EDP_CTRL, 0, BIT(0)),
[RESET_APMU_EDP1] = RESET_DATA(APMU_LCD_EDP_CTRL, 0, BIT(16)),
[RESET_APMU_PCIE_PORTA] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_A, 0,
BIT(5) | BIT(4) | BIT(3)),
[RESET_APMU_PCIE_PORTB] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_B, 0,
BIT(5) | BIT(4) | BIT(3)),
[RESET_APMU_PCIE_PORTC] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_C, 0,
BIT(5) | BIT(4) | BIT(3)),
[RESET_APMU_PCIE_PORTD] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_D, 0,
BIT(5) | BIT(4) | BIT(3)),
[RESET_APMU_PCIE_PORTE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_E, 0,
BIT(5) | BIT(4) | BIT(3)),
[RESET_APMU_PCIE_A_DBI] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_A, 0, BIT(3)),
[RESET_APMU_PCIE_A_SLAVE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_A, 0, BIT(4)),
[RESET_APMU_PCIE_A_MASTER] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_A, 0, BIT(5)),
[RESET_APMU_PCIE_B_DBI] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_B, 0, BIT(3)),
[RESET_APMU_PCIE_B_SLAVE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_B, 0, BIT(4)),
[RESET_APMU_PCIE_B_MASTER] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_B, 0, BIT(5)),
[RESET_APMU_PCIE_C_DBI] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_C, 0, BIT(3)),
[RESET_APMU_PCIE_C_SLAVE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_C, 0, BIT(4)),
[RESET_APMU_PCIE_C_MASTER] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_C, 0, BIT(5)),
[RESET_APMU_PCIE_D_DBI] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_D, 0, BIT(3)),
[RESET_APMU_PCIE_D_SLAVE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_D, 0, BIT(4)),
[RESET_APMU_PCIE_D_MASTER] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_D, 0, BIT(5)),
[RESET_APMU_PCIE_E_DBI] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_E, 0, BIT(3)),
[RESET_APMU_PCIE_E_SLAVE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_E, 0, BIT(4)),
[RESET_APMU_PCIE_E_MASTER] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_E, 0, BIT(5)),
[RESET_APMU_EMAC0] = RESET_DATA(APMU_EMAC0_CLK_RES_CTRL, 0, BIT(1)),
[RESET_APMU_EMAC1] = RESET_DATA(APMU_EMAC1_CLK_RES_CTRL, 0, BIT(1)),
[RESET_APMU_EMAC2] = RESET_DATA(APMU_EMAC2_CLK_RES_CTRL, 0, BIT(1)),
Expand Down
126 changes: 75 additions & 51 deletions include/dt-bindings/reset/spacemit,k3-resets.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -97,62 +97,86 @@
#define RESET_APMU_SDH0 13
#define RESET_APMU_SDH1 14
#define RESET_APMU_SDH2 15
#define RESET_APMU_USB2 16
#define RESET_APMU_USB3_PORTA 17
#define RESET_APMU_USB3_PORTB 18
#define RESET_APMU_USB3_PORTC 19
#define RESET_APMU_USB3_PORTD 20
#define RESET_APMU_QSPI 21
#define RESET_APMU_QSPI_BUS 22
#define RESET_APMU_DMA 23
#define RESET_APMU_AES_WTM 24
#define RESET_APMU_MCB_DCLK 25
#define RESET_APMU_MCB_ACLK 26
#define RESET_APMU_VPU 27
#define RESET_APMU_DTC 28
#define RESET_APMU_GPU 29
#define RESET_APMU_ALZO 30
#define RESET_APMU_MC 31
#define RESET_APMU_CPU0_POP 32
#define RESET_APMU_CPU0_SW 33
#define RESET_APMU_CPU1_POP 34
#define RESET_APMU_CPU1_SW 35
#define RESET_APMU_CPU2_POP 36
#define RESET_APMU_CPU2_SW 37
#define RESET_APMU_CPU3_POP 38
#define RESET_APMU_CPU3_SW 39
#define RESET_APMU_C0_MPSUB_SW 40
#define RESET_APMU_CPU4_POP 41
#define RESET_APMU_CPU4_SW 42
#define RESET_APMU_CPU5_POP 43
#define RESET_APMU_CPU5_SW 44
#define RESET_APMU_CPU6_POP 45
#define RESET_APMU_CPU6_SW 46
#define RESET_APMU_CPU7_POP 47
#define RESET_APMU_CPU7_SW 48
#define RESET_APMU_C1_MPSUB_SW 49
#define RESET_APMU_MPSUB_DBG 50
#define RESET_APMU_UCIE 51
#define RESET_APMU_RCPU 52
#define RESET_APMU_DSI4LN2_ESCCLK 53
#define RESET_APMU_DSI4LN2_LCD_SW 54
#define RESET_APMU_DSI4LN2_LCD_MCLK 55
#define RESET_APMU_DSI4LN2_LCD_DSCCLK 56
#define RESET_APMU_DSI4LN2_DPU_ACLK 57
#define RESET_APMU_DPU_ACLK 58
#define RESET_APMU_UFS_ACLK 59
#define RESET_APMU_EDP0 60
#define RESET_APMU_EDP1 61
#define RESET_APMU_PCIE_PORTA 62
#define RESET_APMU_PCIE_PORTB 63
#define RESET_APMU_PCIE_PORTC 64
#define RESET_APMU_PCIE_PORTD 65
#define RESET_APMU_PCIE_PORTE 66
#define RESET_APMU_USB2_AHB 16
#define RESET_APMU_USB2_VCC 17
#define RESET_APMU_USB2_PHY 18
#define RESET_APMU_USB3_A_AHB 19
#define RESET_APMU_USB3_A_VCC 20
#define RESET_APMU_USB3_A_PHY 21
#define RESET_APMU_USB3_B_AHB 22
#define RESET_APMU_USB3_B_VCC 23
#define RESET_APMU_USB3_B_PHY 24
#define RESET_APMU_USB3_C_AHB 25
#define RESET_APMU_USB3_C_VCC 26
#define RESET_APMU_USB3_C_PHY 27
#define RESET_APMU_USB3_D_AHB 28
#define RESET_APMU_USB3_D_VCC 29
#define RESET_APMU_USB3_D_PHY 30
#define RESET_APMU_QSPI 31
#define RESET_APMU_QSPI_BUS 32
#define RESET_APMU_DMA 33
#define RESET_APMU_AES_WTM 34
#define RESET_APMU_MCB_DCLK 35
#define RESET_APMU_MCB_ACLK 36
#define RESET_APMU_VPU 37
#define RESET_APMU_DTC 38
#define RESET_APMU_GPU 39
#define RESET_APMU_ALZO 40
#define RESET_APMU_MC 41
#define RESET_APMU_CPU0_POP 42
#define RESET_APMU_CPU0_SW 43
#define RESET_APMU_CPU1_POP 44
#define RESET_APMU_CPU1_SW 45
#define RESET_APMU_CPU2_POP 46
#define RESET_APMU_CPU2_SW 47
#define RESET_APMU_CPU3_POP 48
#define RESET_APMU_CPU3_SW 49
#define RESET_APMU_C0_MPSUB_SW 50
#define RESET_APMU_CPU4_POP 51
#define RESET_APMU_CPU4_SW 52
#define RESET_APMU_CPU5_POP 53
#define RESET_APMU_CPU5_SW 54
#define RESET_APMU_CPU6_POP 55
#define RESET_APMU_CPU6_SW 56
#define RESET_APMU_CPU7_POP 57
#define RESET_APMU_CPU7_SW 58
#define RESET_APMU_C1_MPSUB_SW 59
#define RESET_APMU_MPSUB_DBG 60
#define RESET_APMU_UCIE_IP 61
#define RESET_APMU_UCIE_HOT 62
#define RESET_APMU_UCIE_MON 63
#define RESET_APMU_RCPU_AUDIO_SYS 64
#define RESET_APMU_RCPU_MCU_CORE 65
#define RESET_APMU_RCPU_AUDIO_APMU 66
#define RESET_APMU_EMAC0 67
#define RESET_APMU_EMAC1 68
#define RESET_APMU_EMAC2 69
#define RESET_APMU_ESPI_MCLK 70
#define RESET_APMU_ESPI_SCLK 71
#define RESET_APMU_DSI4LN2_ESCCLK 72
#define RESET_APMU_DSI4LN2_LCD_SW 73
#define RESET_APMU_DSI4LN2_LCD_MCLK 74
#define RESET_APMU_DSI4LN2_LCD_DSCCLK 75
#define RESET_APMU_DSI4LN2_DPU_ACLK 76
#define RESET_APMU_DPU_ACLK 77
#define RESET_APMU_UFS_ACLK 78
#define RESET_APMU_EDP0 79
#define RESET_APMU_EDP1 80
#define RESET_APMU_PCIE_A_DBI 81
#define RESET_APMU_PCIE_A_SLAVE 82
#define RESET_APMU_PCIE_A_MASTER 83
#define RESET_APMU_PCIE_B_DBI 84
#define RESET_APMU_PCIE_B_SLAVE 85
#define RESET_APMU_PCIE_B_MASTER 86
#define RESET_APMU_PCIE_C_DBI 87
#define RESET_APMU_PCIE_C_SLAVE 88
#define RESET_APMU_PCIE_C_MASTER 89
#define RESET_APMU_PCIE_D_DBI 90
#define RESET_APMU_PCIE_D_SLAVE 91
#define RESET_APMU_PCIE_D_MASTER 92
#define RESET_APMU_PCIE_E_DBI 93
#define RESET_APMU_PCIE_E_SLAVE 94
#define RESET_APMU_PCIE_E_MASTER 95

/* DCIU resets*/
#define RESET_DCIU_HDMA 0
Expand Down
Loading