Add support for KIT_T2G_B_H_LITE, CYTVII-B-H-8M-320-CPU (with SoC) , KIT_T2G_B_H_EVK (with SoC) , CYTVII-B-E-1M-100-CPU(with SoC CYT2B7),KIT_T2G_B_E_LITE(with SoC CYT2BL))#296
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This reverts commit 807bccd.
Add support for loading CM0+ images within CM7 applications for CAT1C devices. Signed-off-by: Christoph Seitz <christoph.seitz@infineon.com>
Add support for CM0+ sleep image blobs for CYT4DN devices. Signed-off-by: Christoph Seitz <christoph.seitz@infineon.com>
Correct the memory definition in the CYT4DN device and update the memory partitioning on board level. Include support for CM0+ image. Move peripheral definition into common file. Signed-off-by: Christoph Seitz <christoph.seitz@infineon.com>
Add cpu definitions and TCM memory to the main soc dts file. Signed-off-by: Christoph Seitz <christoph.seitz@infineon.com>
This update modifies the device tree for the Infineon kit_t2g_c2d6m_lite to create a new structure to assing memory to different cores. Signed-off-by: Christoph Seitz <christoph.seitz@infineon.com>
This commit removes the configuration options and linker scripts related to the CM0+ image for the CYT4DN series. The changes include the deletion of the CM0+ image RAM and ROM size configurations, as well as the corresponding linker script files. This cleanup is necessary to streamline the build process and eliminate unused configurations. Signed-off-by: Christoph Seitz <christoph.seitz@infineon.com>
This commit introduces Kconfig entries for the Infineon CAT1C M0+ and M7 cores, allowing users to select the appropriate core for their TRAVEO T2G SoC variant. The changes include the addition of core selection options and default configurations based on the selected core. This enhancement improves the configurability of the device tree for the Infineon CAT1C series. Signed-off-by: Christoph Seitz <christoph.seitz@infineon.com>
This commits adds a common base for the CAT1C socs. This includes custom interrupt controller handling to integrate CAT1C system interrupts into zephyr, by placing a fixed vector table into RAM/ROM and to enable zephyr to operator on system interrupts via the IRQ API. Based on the IRQ chages, the SROM infrastructure is initialized during M0+ boot. Signed-off-by: Christoph Seitz <christoph.seitz@infineon.com>
…gration This commit introduces Kconfig support for the M0P launcher image based on the minimal example in the Infineon SOC. It adds necessary configurations in the Kconfig files, ensuring that the M0P launcher can be included in the build process. Additionally, a CMake file is created to handle the sysbuild process for the M0P launcher, setting up the required parameters for the build. These changes are essential for enabling the M0P image integration into M7 builds to access SROM APIs. Signed-off-by: Christoph Seitz <christoph.seitz@infineon.com>
- Introduced device tree source files for the CYT4BF M0+ and M7 cores, including memory regions and CPU configurations. - Added system clock definitions for the CYT4BF series, detailing fixed clocks, PLLs, and clock paths. - Updated CMakeLists to conditionally include QSPI memory slot configuration based on the new Kconfig option. - Modified the SOC vector table to include specific IRQ vector configurations for the CYT4BF series. - Created Kconfig files for the CYT4BF series, defining SOC series, die types, and default configurations. - Updated the SOC YAML file to include CPU cluster definitions for various CYT4BF models.
…Kit T2G Body High Lite
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Add new board basic support. Add Support features : dts, kconfig, defconfig, openocd and doc. Signed-off-by: Shreyas G Khanapur <ShreyasG.Khanapur@infineon.com>
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Enable and configure peripheral support for the kit_t2g-b-h_lite, including multi-core configurations (M0+, M7_0, M7_1). Changes: - Updated board configuration and device tree files for kit_t2g-b-h_lite to enable CAN, Ethernet, Flash, QSPI, and IPC peripherals - Enhanced HAL Infineon module CMake configuration - Configured OpenAMP IPC for dual-core M7_0/M7_1 communication with board-specific overlays and configuration files - Updated SoC IRQ handling and M0+ Kconfig for CAT1C devices - Modified existing driver test samples and network configurations Tested and verified peripherals: - CAN - Ethernet - Flash (SROM API with CM0+ handling) - QSPI - IPM/OpenAMP - HWINFO All peripherals tested successfully on kit_t2g-b-h_lite hardware. Signed-off-by: Nishant-IFX <nishant.kumar@infineon.com>
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Added soc support for CYT2B7 family Added interrupt support and verified with uart and watchdog. Added Board Support for CYTVII-B-E-1M-100-CPU. Signed-off-by: Shreyas G Khanapur <ShreyasG.Khanapur@infineon.com>
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Add new board basic support. Add new Soc support(cyt4bfbche) Add Support features : dts, kconfig, defconfig, openocd and doc. Tested: UART GPIO ADC CAN IPC HWINFO I2C DMA Signed-off-by: Sudeep-IFX <Sudeep.SangahalliDinesh@infineon.com>
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