EE271 - Advanced Digital System Design and Synthesis (Fall 2019)

by Dr. Binh Le

Mainly used language:

Verilog

EDA tools:

• Synopsys Verilog Compiler Simulator (VCS)
• Synopsys Design Compiler (required)
• Cadence NC-Verilog Simulator (optional)

Course Description

This course covers topics in the advanced design and analysis of digital circuits with HDL. The primary goal is to provide in depth understanding of logic and system design, synthesis, and optimization for area, speed and power consumption. The course enables students to apply their knowledge for the design of advanced digital hardware systems with corresponding EDA tools. Verilog HDL will be used for simulation and synthesis of the homework assignments and final design project.