This repository contains a 32-bit, five-stage pipelined RISC-inspired CPU designed and implemented in Verilog for the DE1-SoC FPGA platform. The architecture includes a full pipeline, hazard detection, a register file, ALU, control logic, and integrated peripheral modules such as audio and a display interface.
The processor implements the classic five-stage RISC pipeline:
- Instruction Fetch (IF)
- Instruction Decode (ID)
- Execute (EX)
- Memory Access (MEM)
- Writeback (WB)
The design includes:
- 32-bit datapath
- Register file with controlled writeback
- ALU for arithmetic and logical operations
- Hazard Detection Unit (HDU) for stall insertion
- Pipeline registers between all stages
- Memory and peripheral integration on the DE1-SoC board.
- Audio output unit and display modules
- Design and implementation of the 32-bit, five-stage pipeline
- Program Counter (PC) logic and instruction sequencing
- Instruction Decode and control signal generation
- Register file design and writeback strategy
- ALU implementation and datapath routing
- Hazard Detection Unit (HDU) and stall control
- Pipeline register design for all stages
- Top-level CPU integration and timing coordination
- Debugging pipeline hazards, writeback issues, and instruction sequencing errors
Some peripheral modules and integration tasks were developed in collaboration with teammates. I appreciate their contributions to the overall project environment.
demo/- Demo programdocs/- High-level diagram of the processor.
The full implementation is maintained in a private repository. If you’re interested in reviewing the code or discussing the technical details, feel free to reach out.