This repository documents the problems I have solved on HDLBits.
- Always blocks
- Initial blocks
- Blocking and non-blocking assignments
- Module instantiation
- Port connections
- Hierarchical design
- Generate statements
- Parameters
- Advanced features
- Logic gates
- Multiplexers
- Adders and arithmetic circuits
- Encoders and decoders
- Flip-flops and latches
- Counters
- Shift registers
- Finite State Machines
HDLBits is an interactive learning platform for Verilog HDL. Visit hdlbits.01xz.net to practice.
These solutions are for learning purposes. Try solving problems yourself before looking at solutions.