NASSCOM- RISC-V BASED MYTH PROGRAM

• In this NASSCOM-certified 'RISC-V based MYTH' workshop by VLSI System Design in collaboration with Redwood EDA, I have constructed a RISC-V microarchitecture using the TL-Verilog HDL in the Makerchip IDE, a Design language developed by Redwood EDA.
• Through this workshop I had the opporunity to learn programming in TL-Verilog and also discover the RISC-V ISA,a basic Verification flow in ABI and the basic RISC-V CPU mircoarchitecture. The Makerchip IDE has been used to design, simulate and visualize the circuits.
• Sandbox link: https://myth.makerchip.com/sandbox/0zpfRhB9N/08qh6Vk#