CS56 Final Project: Implementing an RSA key generation and encryption/decryption functionalities on the Basys-3 FPGA Board

Jake Epstein & Matt Kenney

For details, see the PDF, "Digitial Electronics Final Report" and corresponding appendices, "Project Report Appendices." The report covers the purpose of the project, and the functionality of all code modules in detail.

Directory Structure:

Note that the directory structure of this project corresponds to the different types of code files used in VHDL: Design files are the actual "hardware description" files that contribute to the design of the circuitry that results on the FPGA board after synthesis. Simulation files are used for testing the design files. Finally, constraint files specify hardware resources (which buttons, switches, 7-segment displays, etc. we would like to use and how they wire up to various components of our design).