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💻 Green-RISC 🥬

    🕹️ Minimal implementation of a 5 stage pipelined 32 bit RISC V CPU in verilog


Types of instructions in RISC-V arch

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Vector table for determining the type of instruction based on the instr value

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Immediate values decode table (expect for a R instr)

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Few Opcodes (instr[30] + func3 + opcode ) for different instruction

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Overall arch of the CPU implementation

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from learning how to code a microcontroller to actually making one

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