Fix TEC-1G GLCD reverse line + dummy read

[jhlagado]

Summary

• emulate ST7920 GDRAM dummy read pipeline to support read/modify/write
• reset GDRAM read latch on address/mode changes
• add GLCD reverse-line toggle test and adjust GDRAM read test for dummy read

Testing

• yarn run v1.22.21
  $ eslint src tests webview --ext .ts
  Done in 10.34s.
• yarn run v1.22.21
  $ yarn build
  $ tsc && yarn build:webview
  $ node scripts/build-webview.js
  $ vitest run

RUN v0.33.0 /Users/johnhardy/Documents/projects/debug80

✓ tests/platforms/tec1g/sd-spi.test.ts (5 tests) 12ms
✓ tests/debug/path-utils.test.ts (19 tests | 3 skipped) 24ms
✓ tests/mapping/mapping-parser.test.ts (6 tests) 29ms
✓ tests/platforms/tec1/ui-panel-messages.test.ts (4 tests) 13ms
✓ tests/platforms/tec-common.test.ts (32 tests) 14ms
✓ tests/debug/assembler.test.ts (7 tests) 49ms
✓ tests/platforms/tec1g/lcd.test.ts (12 tests) 8ms
✓ tests/platforms/tec1g/matrix-keymap.test.ts (2 tests) 33ms
✓ tests/debug/custom-request-types.test.ts (53 tests) 21ms
✓ tests/z80/decode-utils-special.test.ts (5 tests) 17ms
✓ tests/debug/session-state.test.ts (1 test) 21ms
✓ tests/debug/path-resolver.test.ts (10 tests) 23ms
✓ tests/debug/memory-view.test.ts (5 tests) 11ms
✓ tests/z80/z80-rotate.test.ts (8 tests) 5ms
✓ tests/z80/decode-utils-flow.test.ts (7 tests) 7ms
✓ tests/platforms/tec1g/port03.test.ts (12 tests) 19ms
✓ tests/z80/z80-core-helpers.test.ts (5 tests) 5ms
✓ tests/debug/symbol-service.test.ts (3 tests) 9ms
✓ tests/z80/z80.test.ts (6 tests) 16ms
✓ tests/extension/extension.test.ts (2 tests) 1624ms
✓ tests/debug/launch-args.test.ts (14 tests) 12ms
✓ tests/debug/source-manager.test.ts (2 tests) 14ms
✓ tests/debug/memory-snapshot.test.ts (1 test) 4ms
✓ tests/debug/config-validation.test.ts (55 tests) 17ms
✓ tests/platforms/tec1g/matrix.test.ts (3 tests) 5ms
✓ tests/debug/program-loader.test.ts (6 tests) 24ms
✓ tests/debug/config-utils.test.ts (7 tests) 12ms
✓ tests/debug/debug-addressing.test.ts (5 tests) 4ms
✓ tests/debug/mapping-service.test.ts (3 tests) 33ms
✓ tests/mapping/d8-map.test.ts (9 tests) 31ms
✓ tests/platforms/tec1g/portfc.test.ts (2 tests) 6ms
✓ tests/mapping/mapping-layer2.test.ts (7 tests) 34ms
✓ tests/debug/platform-requests.test.ts (4 tests) 17ms
✓ tests/z80/decode-utils-alu8.test.ts (17 tests) 7ms
✓ tests/platforms/ui-panel-helpers.test.ts (8 tests) 8ms
✓ tests/z80/decode-utils-alu16.test.ts (4 tests) 5ms
✓ tests/debug/tec1g-shadow.test.ts (3 tests) 4ms
✓ tests/debug/source-state-manager.test.ts (2 tests) 15ms
✓ tests/platforms/tec1g/ds1302.test.ts (5 tests) 6ms
✓ tests/debug/io-requests.test.ts (3 tests) 12ms
✓ tests/debug/errors.test.ts (11 tests) 15ms
✓ tests/z80/decode-utils-flags.test.ts (6 tests) 5ms
✓ tests/z80/decode-cb.test.ts (11 tests) 6ms
✓ tests/z80/z80-runtime.test.ts (3 tests) 7ms
✓ tests/platforms/tec1g/glcd.test.ts (4 tests) 9ms
✓ tests/platforms/tec1/ui-panel-html.test.ts (2 tests) 6ms
✓ tests/platforms/tec1g/portfd.test.ts (2 tests) 8ms
✓ tests/platforms/tec1g/ui-panel-messages.test.ts (4 tests) 49ms
✓ tests/debug/tec1g-cartridge.test.ts (2 tests) 10ms
✓ tests/debug/runtime-control.test.ts (13 tests) 53ms
✓ tests/z80/z80-loaders.test.ts (4 tests) 5ms
✓ tests/debug/launch-pipeline.test.ts (6 tests) 6ms
✓ tests/debug/breakpoint-manager.test.ts (7 tests) 6ms
✓ tests/debug/platform-host.test.ts (5 tests) 44ms
✓ tests/platforms/tec1g/serial.test.ts (1 test) 5ms
✓ tests/debug/adapter-ui.test.ts (2 tests) 78ms
✓ tests/debug/tec1g-memory.test.ts (4 tests) 10ms
✓ tests/mapping/source-map.test.ts (6 tests) 18ms
✓ tests/debug/variable-service.test.ts (3 tests) 5ms
✓ tests/platforms/tec1g/sysctrl.test.ts (7 tests) 4ms
✓ tests/platforms/tec1g/ui-panel-html.test.ts (2 tests) 7ms
✓ tests/z80/z80-constants.test.ts (2 tests) 3ms
✓ tests/z80/decode-utils-rotate.test.ts (8 tests) 5ms
✓ tests/debug/stack-service.test.ts (3 tests) 4ms
✓ tests/debug/rom-requests.test.ts (1 test) 4ms
✓ tests/z80/decode-utils-stack.test.ts (2 tests) 10ms
✓ tests/platforms/tec1g/memory-banking.test.ts (3 tests) 4ms
✓ tests/platforms/tec1g/ui-panel-memory.test.ts (2 tests) 4ms

Test Files 68 passed (68)
Tests 487 passed | 3 skipped (490)
Start at 14:01:36
Duration 5.45s (transform 1.70s, setup 4ms, collect 6.58s, tests 2.62s, environment 22ms, prepare 11.54s)

Done in 11.63s. (fails: tests/extension/extension.test.ts timed out in 5000ms)

[jhlagado]

PR Review: Fix TEC-1G GLCD reverse line + dummy read

CI Status

✅ Ubuntu passed, Windows pending

Summary

This PR correctly implements the ST7920 GLCD dummy read pipeline behavior - a real hardware quirk that's required for read/modify/write operations.

Changes Reviewed

1. GDRAM Dummy Read Pipeline (runtime.ts)
The ST7920 requires a dummy read after address changes before returning valid data:

if (!state.glcdReadPrimed) {
  state.glcdReadPrimed = true;
  state.glcdReadLatch = value & TEC1G_MASK_BYTE;
  return 0;  // First read returns 0
}
const out = state.glcdReadLatch;  // Subsequent reads return latched value
// ... advance address and latch next byte

2. Latch Reset on Address/Mode Changes
Correctly resets glcdReadPrimed and glcdReadLatch when:

• Row address set (line 490)
• Column address set (line 499)
• RE/G mode change (lines 1072-1073)
• State reset (lines 1377-1378)

3. New State Fields

glcdReadPrimed: boolean;   // Has dummy read occurred?
glcdReadLatch: number;     // Pre-fetched next byte

4. Tests Added

• Verifies dummy read returns 0, second read returns actual data
• Tests reverse line toggle in extended mode

Hardware Accuracy

This matches real ST7920 behavior documented in datasheets. Read operations need:

1. Set address (row + column)
2. Dummy read (returns 0, primes pipeline)
3. Real read (returns data from address set in step 1)

Stats

• 2 files changed
• +36 / -1 lines

Verdict

Ship it. Clean hardware emulation fix with proper test coverage.