Core performance and size improvement

bram/fx68kRegs_altera.sv

@@ -0,0 +1,88 @@
+module fx68kRegs
+#(
+    parameter FPGA_DEVICE = "Stratix",
+    parameter BRAM_TYPE   = "M4K"
+)
+(
+    input         clk,
+    input         clk_ena,
+
+    input   [4:0] address_a,
+    input         wren_a,
+    input   [3:0] byteena_a,
+    input  [31:0] data_a,
+    output [31:0] q_a,
+
+    input   [4:0] address_b,
+    input         wren_b,
+    input   [3:0] byteena_b,
+    input  [31:0] data_b,
+    output [31:0] q_b
+);
+
+    altsyncram
+    #(
+        .address_aclr_a   ("NONE"),
+        .address_aclr_b   ("NONE"),
+        .address_reg_b    ("CLOCK0"),
+        .byteena_aclr_a   ("NONE"),
+        .byteena_aclr_b   ("NONE"),
+        .byteena_reg_b    ("CLOCK0"),
+        .byte_size        (8),
+        .indata_aclr_a    ("NONE"),
+        .indata_aclr_b    ("NONE"),
+        .indata_reg_b     ("CLOCK0"),
+        .intended_device_family (FPGA_DEVICE),
+        .lpm_type         ("altsyncram"),
+        .numwords_a       (32),
+        .numwords_b       (32),
+        .operation_mode   ("BIDIR_DUAL_PORT"),
+        .outdata_aclr_a   ("NONE"),
+        .outdata_aclr_b   ("NONE"),
+        .outdata_reg_a    ("UNREGISTERED"),
+        .outdata_reg_b    ("UNREGISTERED"),
+        .power_up_uninitialized ("FALSE"),
+        .ram_block_type   (BRAM_TYPE),
+        .read_during_write_mode_mixed_ports ("DONT_CARE"),
+        .widthad_a        (5),
+        .widthad_b        (5),
+        .width_a          (32),
+        .width_b          (32),
+        .width_byteena_a  (4),
+        .width_byteena_b  (4),
+        .wrcontrol_aclr_a ("NONE"),
+        .wrcontrol_aclr_b ("NONE"),
+        .wrcontrol_wraddress_reg_b ("CLOCK0")
+    )
+    U_altsyncram
+    (
+        // Clock & reset
+        .aclr0            (1'b0),
+        .aclr1            (1'b0),
+        .clock0           (clk),
+        .clock1           (1'b1),
+        .clocken0         (clk_ena),
+        .clocken1         (1'b1),
+        .clocken2         (1'b1),
+        .clocken3         (1'b1),
+        // Port A
+        .rden_a           (1'b1),
+        .wren_a           (wren_a),
+        .byteena_a        (byteena_a),
+        .address_a        (address_a),
+        .addressstall_a   (1'b0),
+        .data_a           (data_a),
+        .q_a              (q_a),
+        // Port B
+        .rden_b           (1'b1),
+        .wren_b           (wren_b),
+        .byteena_b        (byteena_b),
+        .address_b        (address_b),
+        .addressstall_b   (1'b0),
+        .data_b           (data_b),
+        .q_b              (q_b),
+
+        .eccstatus        ()
+    );
+
+endmodule

bram/fx68kRegs_generic.sv

@@ -0,0 +1,97 @@
+module fx68kRegs
+(
+    input         clk,
+    input         clk_ena,
+
+    input   [4:0] address_a,
+    input         wren_a,
+    input   [3:0] byteena_a,
+    input  [31:0] data_a,
+    output [31:0] q_a,
+
+    input   [4:0] address_b,
+    input         wren_b,
+    input   [3:0] byteena_b,
+    input  [31:0] data_b,
+    output [31:0] q_b
+);
+
+//=============================================================================
+// Inferred blocks RAM
+//=============================================================================
+
+    logic [15:0] ram_L [0:31];
+    logic [ 7:0] ram_W [0:31];
+    logic [ 7:0] ram_B [0:31];
+
+//=============================================================================
+// Port A access
+//=============================================================================
+
+    reg [31:0] r_q_a;
+
+    always_ff @(posedge clk) begin : PORT_A
+
+        if (clk_ena) begin
+            if (byteena_a[2] & wren_a) begin
+                ram_L[address_a] <= data_a[31:16];
+                r_q_a[31:16] <= data_a[31:16];
+            end
+            else begin
+                r_q_a[31:16] <= ram_L[address_a];
+            end
+            if (byteena_a[1] & wren_a) begin
+                ram_W[address_a] <= data_a[15: 8];
+                r_q_a[15: 8] <= data_a[15: 8];
+            end
+            else begin
+                r_q_a[15: 8] <= ram_W[address_a];
+            end
+            if (byteena_a[0] & wren_a) begin
+                ram_B[address_a] <= data_a[ 7: 0];
+                r_q_a[ 7: 0] <= data_a[ 7: 0];
+            end
+            else begin
+                r_q_a[ 7: 0] <= ram_B[address_a];
+            end
+        end
+    end
+
+    assign q_a = r_q_a;
+
+//=============================================================================
+// Port B access
+//=============================================================================
+
+    reg [31:0] r_q_b;
+
+    always_ff @(posedge clk) begin : PORT_B
+
+        if (clk_ena) begin
+            if (byteena_b[2] & wren_b) begin
+                ram_L[address_b] <= data_b[31:16];
+                r_q_b[31:16] <= data_b[31:16];
+            end
+            else begin
+                r_q_b[31:16] <= ram_L[address_b];
+            end
+            if (byteena_b[1] & wren_b) begin
+                ram_W[address_b] <= data_b[15: 8];
+                r_q_b[15: 8] <= data_b[15: 8];
+            end
+            else begin
+                r_q_b[15: 8] <= ram_W[address_b];
+            end
+            if (byteena_b[0] & wren_b) begin
+                ram_B[address_b] <= data_b[ 7: 0];
+                r_q_b[ 7: 0] <= data_b[ 7: 0];
+            end
+            else begin
+                r_q_b[ 7: 0] <= ram_B[address_b];
+            end
+        end
+    end
+
+    assign q_b = r_q_b;
+
+endmodule

bram/fx68kRom_altera.sv

@@ -0,0 +1,64 @@
+module fx68kRom
+#(
+    parameter bit     OUTPUT_REG  = 1,
+    parameter integer ADDR_WIDTH  = 10,
+    parameter integer DATA_WIDTH  = 32,
+    parameter         INIT_FILE   = "NONE",
+    parameter         FPGA_DEVICE = "Stratix",
+    parameter         BRAM_TYPE   = "M4K"
+)
+(
+    input                   rst,
+    input                   clk,
+    input                   clk_ena,
+    input  [ADDR_WIDTH-1:0] addr,
+    output [DATA_WIDTH-1:0] q
+);
+
+    altsyncram
+    #(
+        .address_aclr_a  ("NONE"),
+        .init_file       (INIT_FILE),
+        .intended_device_family (FPGA_DEVICE),
+        .lpm_hint        ("ENABLE_RUNTIME_MOD=NO"),
+        .lpm_type        ("altsyncram"),
+        .numwords_a      (1 << ADDR_WIDTH),
+        .operation_mode  ("ROM"),
+        .outdata_aclr_a  ((OUTPUT_REG) ? "CLEAR1" : "NONE"),
+        .outdata_reg_a   ((OUTPUT_REG) ? "CLOCK1" : "UNREGISTERED"),
+        .ram_block_type  (BRAM_TYPE),
+        .widthad_a       (ADDR_WIDTH),
+        .width_a         (DATA_WIDTH),
+        .width_byteena_a (1)
+    )
+    U_altsyncram
+    (
+        .aclr0           (1'b0),
+        .aclr1           ((OUTPUT_REG) ? rst : 1'b0),
+        .clock0          (clk),
+        .clock1          ((OUTPUT_REG) ? clk : 1'b1),
+        .clocken0        (1'b1),
+        .clocken1        ((OUTPUT_REG) ? clk_ena : 1'b1),
+        .clocken2        (1'b1),
+        .clocken3        (1'b1),
+
+        .address_a       (addr),
+        .addressstall_a  (1'b0),
+        .rden_a          (1'b1),
+        .wren_a          (1'b0),
+        .byteena_a       (1'b1),
+        .data_a          ({DATA_WIDTH{1'b1}}),
+        .q_a             (q),
+
+        .address_b       (1'b1),
+        .addressstall_b  (1'b0),
+        .rden_b          (1'b1),
+        .wren_b          (1'b0),
+        .byteena_b       (1'b1),
+        .data_b          (1'b1),
+        .q_b             (/* open */),
+
+        .eccstatus       (/* open */)
+    );
+
+endmodule

bram/fx68kRom_generic.sv

@@ -0,0 +1,68 @@
+module fx68kRom
+#(
+    parameter bit     OUTPUT_REG = 1,
+    parameter integer ADDR_WIDTH = 10,
+    parameter integer DATA_WIDTH = 32,
+    parameter string  INIT_FILE  = "NONE"
+)
+(
+    input                   rst,
+    input                   clk,
+    input                   clk_ena,
+    input  [ADDR_WIDTH-1:0] addr,
+    output [DATA_WIDTH-1:0] q
+);
+
+//=============================================================================
+// Inferred ROM block
+//=============================================================================
+
+    logic [DATA_WIDTH-1:0] rom [0:(1 << ADDR_WIDTH)-1];
+
+//=============================================================================
+// ROM content
+//=============================================================================
+
+    initial begin : ROM_INIT
+        integer i;
+
+        if (INIT_FILE == "NONE") begin
+            for (i = 0; i < (1 << ADDR_WIDTH); i = i + 1) begin
+                rom[i] = {DATA_WIDTH{1'b0}};
+            end
+        end
+        else begin
+            $readmemb(INIT_FILE, rom);
+        end
+    end
+
+//=============================================================================
+// ROM read
+//=============================================================================
+
+    reg [DATA_WIDTH-1:0] r_rom_q_p0;
+
+    always_ff @(posedge clk) begin : ROM_READ_P0
+
+        r_rom_q_p0 <= rom[addr];
+    end
+
+//=============================================================================
+// Asynchronous reset on registered output
+//=============================================================================
+
+    reg [DATA_WIDTH-1:0] r_rom_q_p1;
+
+    always_ff @(posedge rst or posedge clk) begin : OUTPUT_REG_P1
+
+        if (rst) begin
+            r_rom_q_p1 <= {DATA_WIDTH{1'b0}};
+        end
+        else if (clk_ena) begin
+            r_rom_q_p1 <= r_rom_q_p0;
+        end
+    end
+
+    assign q = (OUTPUT_REG) ? r_rom_q_p1 : r_rom_q_p0;
+
+endmodule