This repo is associated with Computer Architecture Lab Assignments for the Spring 2023 session of CSED311 @ POSTECH. This course dives into the depth of computer architecture, covering key concepts such as CPU, Cache, and Memory.
The lab assignments are implemented in Verilog and traverse various facets of computer architecture:
- Lab 1: Arithmetic Logic Unit (ALU) and Vending Machine
- Lab 2: Single-Cycle CPU
- Lab 3: Multi-Cycle CPU
- Lab 4: 5-Stage Pipelined CPU
- Lab 4-1: Without control flow
- Lab 4-2: With control flow
- Lab 5: CPU with Cache Memory (Developed from Lab 4)
Each lab builds upon the knowledge and skills developed in the previous one, gradually increasing in complexity and requiring a comprehensive understanding of computer architecture concepts.
Please be advised that the code provided might contain minor errors. Always cross-check with your understanding and learning material before utilizing the code for your projects or studies.
These lab assignments was bulit as a team. Special thanks to my teammate Taehyeok Ha