Welcome to the repository for the Digital System Design Lab Assignments for the Spring 2022 session of CSED273 @ POSTECH! This course dives into the the basic computer architecture and basic computer circuits covering key concepts such as 2's complement, Adder, MUX, Flip-Flop, and FSM.
The lab assignments are implemented in Verilog. Here's the overview below:
- Lab 1: Basic Logic Circuit
- Lab 2: Boolean Algebra
- Lab 3: Decoder and Multiplexer
- Lab 4: Binary Arithmetic
- Lab 5: ALU and JKFF
- Lab 6: Sequential Circuit Counter
- Final Project: Simple Moore or Mealy Machine and its Application
Each lab builds upon the knowledge and skills developed in the previous one, gradually increasing in complexity and requiring a comprehensive understanding of concepts
Please be advised that the code provided might contain minor errors. Always cross-check with your understanding and learning material before utilizing the code for your projects or studies.
These lab assignments was bulit on my own. However, final project was a team project. Special thanks to my teammates Jeongin Jang and Taehyeok Ha.