Hardware-native static site generation in RISC-V Assembly. "Baremetal" — No OS, no runtime, no abstractions. A generator that treats site synthesis as a formal sequence of register-level operations.
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Firmware Engineers targeting ASICs and Edge tech where every byte of overhead is a failure.
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Low-level purists who want to generate site content directly from bootloaders or custom silicon.
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Systems Architects requiring an engine that can run on a RISC-V soft-core within an FPGA without a kernel.
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Security Researchers needing a generator with a zero-syscall attack surface.
baremetal-ssg is written in pure RISC-V assembly (rv64gc). Site generation is reduced to a series of atomic memory moves and integer operations, bypassing the "bloat" of even the most efficient C compilers.
Designed to run on the metal. It manages its own memory and I/O, making it the fastest possible generator for high-integrity Edge hardware where a kernel is an unnecessary security risk.
Templates are not parsed; they are memory-mapped. By treating content as a series of offsets, baremetal-ssg achieves true
# Assemble the core using the RISC-V toolchain via asdf
just setup
# Flash the generator logic to the target ASIC or Simulator
just flash
# Build the site directly on the hardware (Zero-OS mode)
just build-hardware-
O(1) Memory Management - Manual stack and heap control for absolute predictability.
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Zero-Runtime Overhead - No garbage collection, no heap-fragmentation, no hidden control flow.
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Podman-First Simulation - Test assembly logic in a QEMU-driven Podman container.
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Accessibility - Hardware-accelerated metadata tagging for BSL, GSL, and Makaton.
