A Unified OpenCL-flavor Programming Model with Scalable Hybrid Hardware Platform on FPGAs
The design flow is tested under Windows 7 64 bits with Cygwin installed and Python 2.7. I used Xilinx Vivado 2014.2 with full installation. Linux is not tested. But if you want to use Linux you might need to modify some of the scripts. No matter Windows or Linux is used, be sure you have added the Vivado, and sdk executable directories to your PATH variable.
Xilinx KC705 is tested. ZC706 and VC707 with off-chip memory should also work. But you need figure out a way to use UART in PL part when using ZC706 since current HOpenCL will not use its ARM processors.
- Generate hardware kernels. If you do not want to add hardware kernels to the system, this step can be ignored. We use Vivado HLS tools to generate hardware IPs. Create an HLS project and add the HLS source file in the zip file to your project. Make sure that the top function name is the same with one in HLS source file. Then, click synthesis button and export IPs.
- Generate supporting IPs. Besides hardware kernels, there are other IPs that need to be generated by HLS tools. Under the supportedIPs in the zip file, there are several HLS source files. You need to create the corresponding HLS projects one by one, and synthesis and export IPs. Make sure the top function names are the same with those in the HLS source files.
- Build hardware platform. In this step, we will generate a hardware platform where hardware kernels and software kernels can run. Create a blank Vivado project. You need to add the IP repository to include your all your IPs (i.e. hardware kernels, and supported IPs). Change the numGroup (number of groups), numGPP (number of general-purpose processors), and numACC (number of accelerators) in the top the TCL file generate_system.tcl. You can either source the tcl file in Vivado TCL console or simply paste into the console. After generating, you need to generate products, and generate HDL wrapper. Finally, click generate bitstream.
- Generate and compile SDK projects. Since all slaves are symmetric to each other, you can either build only one SDK project or different SDK projects for all slaves. Please check the instructions in script config_sdk.py. Make sure that the src folder is in the same folder with config_sdk.py.
- Download bits to FPGA. Follow the instructions in file download.py. After downloading, results will be displayed on the UART console.