Note: This is a side of Nijigasaki IC Design Club

We will provide some open-source free-to-use ASIC/FPGA IP cores, modules, design projects for everyone!

This repository provides a collection of Mordern System Verilog infrastructure components for RTL design and Verification, focusing on scalability, modularity, and maintainability. Each module is designed to simplify integration and promote best practices across different hardware projects.

We use FuseSoC to manage dependencies and relationships between components. FuseSoC allows easy reuse, configuration, and simulation of IP blocks across projects. You can also use FuseSoC to integrate our components directly into your design, ensuring a consistent and automated build flow.

All components in this library follow a clean and unified coding style, with high readability and synthesizability in mind. Under the MIT License, you are free to:

• Modify the functions or designs as you wish.
• Integrate them into commercial or academic projects.
• Contribute improvements or bug fixes back to the community.

We warmly welcome community contributions! If you’d like to improve a design, add a new feature, or share your own module:

• Fork the repository you want to edit.
• Make your changes and test them.
• Submit a pull request with a clear description.

We review all contributions carefully to maintain design quality and consistency.