Pengembangan Sistem Frequency Analyzer Digital Berbasis Fast Fourier Transform 64-Titik Radix-2 pada FPGA Cyclone IV untuk Optimasi Zero-Crossing Switching
Project Assigned by: Nana Sutisna,. S.T., M.T., Ph.D.
- Muhammad Adli Syauqi (13224082)
- Muhammad Ammar Hanif (13224087)
- Moch Dimas Ristanto (13224083)
The working version are the one inside v5_32_16 (32 POINT, 16 bit per POINT) and v5_64_8 (64 POINT, 8 bit per POINT).
Note that there's a bug for v5_32_16 the version, because it can output the correct and false output randomly (with the same exact input). Therefore, to get the correct output, just retry uploading the input until you get the similar output as the expected output.
The main revision was to use the memory-based architecture rather than the SDF architecture. This change has to be done because of the Logic Element (LE) limitation in the Cyclone IV FPGA.