This repository contains an implementation for a RISC-V processor to run on a Spartan-7 FPGA. The architecture is a 5-stage pipeline with a shared instruction and data memory. The CPU supports the RV32I base instruction set.
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My custom RISC-V core in SystemVerilog
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griffinross2/RISC-V-Core
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My custom RISC-V core in SystemVerilog
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