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RISC-V: gate __builtin_ctzll behind Zbb to avoid 10 % slowdown #214

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Merged
danilak-G merged 5 commits into from
Nov 20, 2025
Merged

RISC-V: gate __builtin_ctzll behind Zbb to avoid 10 % slowdown #214

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727f5b3
add zbb check macro
anthony-zy Nov 10, 2025
30dbdc2
add zbb check macro
anthony-zy Nov 10, 2025
c633c6b
Resolve merge conflicts
anthony-zy Nov 10, 2025
992fb9f
Resolve merge conflicts
anthony-zy Nov 10, 2025
a862a74
fix confic
anthony-zy Nov 10, 2025
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16 changes: 13 additions & 3 deletions CMakeLists.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -155,10 +155,20 @@ int main() {
return __builtin_expect(0, 1);
}" HAVE_BUILTIN_EXPECT)

# Check if the built-in __builtin_ctz (count trailing zeros) is available.
# Require either a non-RISC-V target, or a RISC-V core that implements
# the Zbb bit-manipulation extension where ctz is guaranteed.
check_cxx_source_compiles("
int main() {
return __builtin_ctzll(0);
}" HAVE_BUILTIN_CTZ)
#ifdef __riscv
#ifdef __riscv_zbb
int main() { return __builtin_ctzll(0); }
#else
#error \"ZBB not enabled in current config\"
#endif
#else
int main() { return __builtin_ctzll(0); }
#endif
" HAVE_BUILTIN_CTZ)

check_cxx_source_compiles("
int main() {
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3 changes: 2 additions & 1 deletion snappy-stubs-internal.h
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Original file line number Diff line number Diff line change
Expand Up @@ -304,8 +304,8 @@ class Bits {
void operator=(const Bits&);
};

// In RISC-V, CLZ is supported by instructions from the ZBB bit-manipulation extension.
#if HAVE_BUILTIN_CTZ

inline int Bits::Log2FloorNonZero(uint32_t n) {
assert(n != 0);
// (31 ^ x) is equivalent to (31 - x) for x in [0, 31]. An easy proof
Expand Down Expand Up @@ -393,6 +393,7 @@ inline int Bits::FindLSBSetNonZero(uint32_t n) {

#endif // End portable versions.

// In RISC-V, CLZ is supported by instructions from the ZBB bit-manipulation extension.
#if HAVE_BUILTIN_CTZ

inline int Bits::FindLSBSetNonZero64(uint64_t n) {
Expand Down