Add Wishbone burst support to HPS NXLRAM interface #533
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Thanks @koluckirafal! Please see https://github.com/google/CFU-Playground/pull/533/checks?check_run_id=6080471949 . Ask your Antmicro colleagues if you have any questions about that. |
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@koluckirafal can you rebase this on current main when you get a chance? |
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This branch is not working correctly for me on the proto2 board, before or after the rebase.
One possible way to debug would be trying the |
This commit adds support for incrementing address burst cycles in NXLRAM Wishbone interface. Ported from enjoy-digital/litex#1267 Signed-off-by: Rafal Kolucki <rkolucki@antmicro.com>
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This PR adds support for incrementing address burst cycles in NXLRAM Wishbone interface in HPS SoC, which allows for faster reading of data in case of e.g. cache misses.
This change is ported from LiteX, but with burst mode permamently enabled, so it doesn't require updated LiteX: enjoy-digital/litex#1267