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riscv64: add disassembly support and tests for zacas #17

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riscv64: add disassembly support and tests for zacas #17

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4 changes: 3 additions & 1 deletion riscv64/riscv64asm/plan9x.go
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Original file line number Diff line number Diff line change
Expand Up @@ -48,7 +48,9 @@ func GoSyntax(inst Inst, pc uint64, symname func(uint64) (string, uint64), text

case AMOADD_D, AMOADD_D_AQ, AMOADD_D_RL, AMOADD_D_AQRL, AMOADD_W, AMOADD_W_AQ,
AMOADD_W_RL, AMOADD_W_AQRL, AMOAND_D, AMOAND_D_AQ, AMOAND_D_RL, AMOAND_D_AQRL,
AMOAND_W, AMOAND_W_AQ, AMOAND_W_RL, AMOAND_W_AQRL, AMOMAXU_D, AMOMAXU_D_AQ,
AMOAND_W, AMOAND_W_AQ, AMOAND_W_RL, AMOAND_W_AQRL, AMOCAS_D, AMOCAS_D_AQ,
AMOCAS_D_AQRL, AMOCAS_D_RL, AMOCAS_Q, AMOCAS_Q_AQ, AMOCAS_Q_AQRL, AMOCAS_Q_RL,
AMOCAS_W, AMOCAS_W_AQ, AMOCAS_W_AQRL, AMOCAS_W_RL, AMOMAXU_D, AMOMAXU_D_AQ,
AMOMAXU_D_RL, AMOMAXU_D_AQRL, AMOMAXU_W, AMOMAXU_W_AQ, AMOMAXU_W_RL, AMOMAXU_W_AQRL,
AMOMAX_D, AMOMAX_D_AQ, AMOMAX_D_RL, AMOMAX_D_AQRL, AMOMAX_W, AMOMAX_W_AQ, AMOMAX_W_RL,
AMOMAX_W_AQRL, AMOMINU_D, AMOMINU_D_AQ, AMOMINU_D_RL, AMOMINU_D_AQRL, AMOMINU_W,
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48 changes: 48 additions & 0 deletions riscv64/riscv64asm/tables.go
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12 changes: 12 additions & 0 deletions riscv64/riscv64asm/testdata/gnucases.txt
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Expand Up @@ -19,6 +19,18 @@ afb26362| amoand.d.rl x5,x6,(x7)
afa26360| amoand.w x5,x6,(x7)
afa26364| amoand.w.aq x5,x6,(x7)
afa26362| amoand.w.rl x5,x6,(x7)
afa2632e| amocas.w.aqrl x5,x6,(x7)
afa2632c| amocas.w.aq x5,x6,(x7)
afa2632a| amocas.w.rl x5,x6,(x7)
afa26328| amocas.w x5,x6,(x7)
afb2632e| amocas.d.aqrl x5,x6,(x7)
afb2632c| amocas.d.aq x5,x6,(x7)
afb2632a| amocas.d.rl x5,x6,(x7)
afb26328| amocas.d x5,x6,(x7)
afc2632e| amocas.q.aqrl x5,x6,(x7)
afc2632c| amocas.q.aq x5,x6,(x7)
afc2632a| amocas.q.rl x5,x6,(x7)
afc26328| amocas.q x5,x6,(x7)
afb263e0| amomaxu.d x5,x6,(x7)
afb263e4| amomaxu.d.aq x5,x6,(x7)
afb263e2| amomaxu.d.rl x5,x6,(x7)
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12 changes: 12 additions & 0 deletions riscv64/riscv64asm/testdata/plan9cases.txt
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Expand Up @@ -19,6 +19,18 @@ afb26362| AMOANDD X6, (X7), X5
afa26360| AMOANDW X6, (X7), X5
afa26364| AMOANDW X6, (X7), X5
afa26362| AMOANDW X6, (X7), X5
afa2632e| AMOCASW X6, (X7), X5
afa2632c| AMOCASW X6, (X7), X5
afa2632a| AMOCASW X6, (X7), X5
afa26328| AMOCASW X6, (X7), X5
afb2632e| AMOCASD X6, (X7), X5
afb2632c| AMOCASD X6, (X7), X5
afb2632a| AMOCASD X6, (X7), X5
afb26328| AMOCASD X6, (X7), X5
afc2632e| AMOCASQ X6, (X7), X5
afc2632c| AMOCASQ X6, (X7), X5
afc2632a| AMOCASQ X6, (X7), X5
afc26328| AMOCASQ X6, (X7), X5
afb263e0| AMOMAXUD X6, (X7), X5
afb263e4| AMOMAXUD X6, (X7), X5
afb263e2| AMOMAXUD X6, (X7), X5
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2 changes: 2 additions & 0 deletions riscv64/riscv64spec/spec.go
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Expand Up @@ -32,6 +32,7 @@ var extensions = []string{
"rv_m",
"rv_q",
"rv_v",
"rv_zacas",
"rv_zba",
"rv_zbb",
"rv_zbs",
Expand All @@ -46,6 +47,7 @@ var extensions = []string{
"rv64_i",
"rv64_m",
"rv64_q",
"rv64_zacas",
"rv64_zba",
"rv64_zbb",
"rv64_zbs",
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