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Papilio Schematic Library - Schematic System on Chip (Source Code) - Current Version 1.2

Papilio SOC Home Page
http://papilio.cc

CHANGELOG
11/21/2013 Version 1.2
	-Support for Papilio One 250K board.
	-Base template projects were consolidated into a single directory.
	-The order of the Wing slots on the hardware symbols were re-ordered to be more user friendly.
	-Symbols were renamed to look nicer in a list.
	-Clocks were added to the soft processor symbols.
	-All VHDL files moved into libraries.

11/5/2013 Version 1.1
	-Wishbone buses were streamlined down to two connections.
	-Symbols were renamed and Symbol Library re-organized.
	-Wings A, B, and C were broken down from buses into individual pins.

9/12/2013 Version 1.0
	Initial Release

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A library of Soft Processors and peripherals that can be used with Webpack schematic editor to build a custom SOC for the Papilio

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  • VHDL 78.1%
  • Eagle 17.2%
  • Verilog 3.7%
  • Other 1.0%