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R5900 multimedia instructions (MMI)
The R5900 has a set of multimedia instructions (MMIs) operating on the 128-bit general purpose registers (GPRs). Each register is partitioned into parallel integer fields of 16×8 bits, 8×16 bits, 4×32 bits, or 2×64 bits, or floating-point fields of 4×32 bits, depending on the instruction.
The R5900 MMI architecture is similar to the MIPS SIMD architecture (MSA). Comparison of notable features:
| R5900 MMI | MIPS SIMD (MSA) | |
|---|---|---|
| Vector registers | 32 GPRs (aliased) | 32 FPRs (aliased) |
| Vector width | 128 bits | 128 bits |
| IEEE 754 compliant | no | yes |
| Access | Always enabled | ? |
Review the R5900 floating point unit (FPU) for its IEEE 754 noncompliance.
The base o32 and n32 MIPS ABIs for the R5900 are extended to allow use of R5900 MMIs. The ABI extension is compatible with the base ABIs in the sense that o32 and n32 machine code link and execute unchanged on systems supporting R5900 MMIs. In particular, the extension doesn’t change base ABI data type layouts, alignments, nor calling conventions (including callee-saved, call-clobbered (temporary) or callee-saved status of aliased GPRs). However, vector data types are considered part of the extended R5900 MMI ABI.
As a consequence, compiling for R5900 MMIs doesn’t change base ABI vector calling conventions. Vector data types passed and returned by value don’t use the MMI vector registers. Rather, passing and returning vectors by value follow the calling conventions of the base ABI.
Review issues #3 and #5 for more details.
Tip
The base ABIs may seem to handle vectors inefficiently. However, compiler interprocedural optimisation should recover such performance losses.
FIXME: What link time optimisation (LTO) etc. options to use?
Autovectorisation support for both GCC and LLVM compilers is in progress. LLVM is expected to be significantly more efficient in using the ACC registers.
FIXME: What compiler options to use?