Skip to content
View evasilly's full-sized avatar

Block or report evasilly

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don't include any personal information such as legal names or email addresses. Markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Pinned Loading

  1. jtagBIST jtagBIST Public

    SystemVerilog 1

  2. jtagSys jtagSys Public

    SystemVerilog

  3. scr1 scr1 Public

    Forked from syntacore/scr1

    SCR1 is a high-quality open-source RISC-V MCU core in Verilog

    SystemVerilog 1

  4. sdk_led sdk_led Public

    C

  5. sdk_rtos sdk_rtos Public

    C

  6. practice practice Public