build/amaranth2v_converter.py: amaranth wrapper

[trabucayre]

It may be useful to integrate cores written in amaranth-lang into LiteX gateware.

This has already been demonstrated in
litecompute_sdr_poc using simple modules. However, the approach used there is not generic enough. In particular, when the inferred core requires one or more clock domains, this approach no longer works and requires writing an additional Amaranth Module to create the missing pieces.

The Amaranth2VConverter is based on the orbtrace wrapper. The goal is to provide a more generic way to bridge Amaranth and LiteX/Migen, following a model similar to Instance and VHD2VConverter.

Main features:

• At constructor time an Amaranth module is created to handle both clock domains and module provided by the user/caller
• It takes a list of (Amaranth Signal, Migen Signal) pairs instead of a classic dictionary mapping signal names to Migen signals.
• A list of clock domains can be provided either at construction time or later.
• It writes out the Verilog generated by Amaranth.
• It creates a LiteX Instance to integrate the generated Verilog into the LiteX gateware.

Example usage

[...]

# Luna/USBSerialDevice ---------------------------------------------------------------------
self.usb = usb = luna.full_devices.USBSerialDevice(bus=ulpi, idVendor=0x1209, idProduct=0x0001)
[...]

# Connections ------------------------------------------------------------------------------
self.conn_list += [
    [...]
    # Source.
    # -------
    (usb.rx.valid,   source.valid),
    (usb.rx.ready,   source.ready),
    (usb.rx.last,    source.last),
    (usb.rx.first,   source.first),
    (usb.rx.payload, source.data),
]
[...]

# Amaranth Converter -----------------------------------------------------------------------
self.converter = Amaranth2VConverter(self.platform,
    name          = "usb_cdc_acm",
    module        = self.usb,
    conn_list     = self.conn_list,
    clock_domains = self.cd_list,
    output_dir    = None,
)