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Shell/4437 3 #108

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3591ade
Revert "USB: Switch to NOP FIQ"
Dec 9, 2015
9abeb99
remove mphi dependency
Dec 17, 2015
3965ecd
re-enable haintmsk for the host channel which have finished last inte…
Dec 22, 2015
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2 changes: 1 addition & 1 deletion drivers/amlogic/usb/dwc_otg/310/dwc_otg_driver.c
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Original file line number Diff line number Diff line change
Expand Up @@ -276,7 +276,7 @@ static const char *dma_config_name[] = {
//Global variable to switch the fiq fix on or off
bool fiq_enable = 1;
// Global variable to enable the split transaction fix
bool fiq_fsm_enable = false;
bool fiq_fsm_enable = true;
//Bulk split-transaction NAK holdoff in microframes
uint16_t nak_holdoff = 8;

Expand Down
34 changes: 15 additions & 19 deletions drivers/amlogic/usb/dwc_otg/310/dwc_otg_fiq_fsm.c
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Expand Up @@ -1172,6 +1172,15 @@ void notrace __dwc_otg_fiq_fsm(struct fiq_state *state, int num_channels)
int i;
haint.d32 = FIQ_READ(state->dwc_regs_base + HAINT);
haintmsk.d32 = FIQ_READ(state->dwc_regs_base + HAINTMSK);

// check the host channel intr been handled or not. if yes, allow
// interrupt trigger.
for (i = 0; i < num_channels; i++) {
if (state->channel[i].hcint_handled) {
haintmsk.d32 |= (1 << i);
state->channel[i].hcint_handled = 0;
}
}
haint.d32 &= haintmsk.d32;
haint_handled.d32 = 0;
for (i=0; i<num_channels; i++) {
Expand Down Expand Up @@ -1204,6 +1213,7 @@ void notrace __dwc_otg_fiq_fsm(struct fiq_state *state, int num_channels)
FIQ_WRITE(state->dwc_regs_base + HAINTMSK, haintmsk.d32);
kick_irq |= 1;
}

/* Top-Level interrupt - always handled because it's level-sensitive */
gintsts_handled.b.hcintr = 1;
}
Expand All @@ -1216,9 +1226,6 @@ void notrace __dwc_otg_fiq_fsm(struct fiq_state *state, int num_channels)
gintmsk.d32 &= state->gintmsk_saved.d32;
gintmsk.b.sofintr = 1;
FIQ_WRITE(state->dwc_regs_base + GINTMSK, gintmsk.d32);
// fiq_print(FIQDBG_INT, state, "KICKGINT");
// fiq_print(FIQDBG_INT, state, "%08x", gintmsk.d32);
// fiq_print(FIQDBG_INT, state, "%08x", state->gintmsk_saved.d32);
kick_irq |= 1;
}

Expand All @@ -1227,13 +1234,6 @@ void notrace __dwc_otg_fiq_fsm(struct fiq_state *state, int num_channels)
FIQ_WRITE(state->dwc_regs_base + GINTSTS, gintsts_handled.d32);
}

/* We got an interrupt, didn't handle it. */
//if (kick_irq) {
// state->mphi_int_count++;
// FIQ_WRITE(state->mphi_regs.outdda, (int) state->dummy_send);
// FIQ_WRITE(state->mphi_regs.outddb, (1<<29));

//}
state->fiq_done++;
if (kick_irq)
WRITE_CBUS_REG(ISA_TIMERD, 1);
Expand Down Expand Up @@ -1293,15 +1293,11 @@ void notrace dwc_otg_fiq_nop(struct fiq_state *state)

/* We got an interrupt, didn't handle it and want to mask it */
if (~(state->gintmsk_saved.d32)) {
// state->mphi_int_count++;
gintmsk.d32 &= state->gintmsk_saved.d32;
FIQ_WRITE(state->dwc_regs_base + GINTMSK, gintmsk.d32);
/* Force a clear before another dummy send */
// FIQ_WRITE(state->mphi_regs.intstat, (1<<29));
// FIQ_WRITE(state->mphi_regs.outdda, (int) state->dummy_send);
// FIQ_WRITE(state->mphi_regs.outddb, (1<<29));
state->fiq_done++;
WRITE_CBUS_REG(ISA_TIMERD, 1);
gintmsk.d32 &= state->gintmsk_saved.d32;
FIQ_WRITE(state->dwc_regs_base + GINTMSK, gintmsk.d32);

state->fiq_done++;
WRITE_CBUS_REG(ISA_TIMERD, 1);
}
//mb();
}
Expand Down
1 change: 1 addition & 0 deletions drivers/amlogic/usb/dwc_otg/310/dwc_otg_fiq_fsm.h
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Expand Up @@ -289,6 +289,7 @@ struct fiq_channel_state {
unsigned int expected_uframe;
/* in/out for communicating number of dma buffers used, or number of ISOC to do */
unsigned int nrpackets;
unsigned int hcint_handled;
struct fiq_dma_info dma_info;
struct fiq_hs_isoc_info hs_isoc_info;
/* Copies of HC registers - in/out communication from/to IRQ handler
Expand Down
2 changes: 2 additions & 0 deletions drivers/amlogic/usb/dwc_otg/310/dwc_otg_hcd.c
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Expand Up @@ -1083,6 +1083,7 @@ int dwc_otg_hcd_init(dwc_otg_hcd_t * hcd, dwc_otg_core_if_t * core_if)
dwc_otg_hcd_free(hcd);
goto out;
}
memset(channel, 0, sizeof(dwc_hc_t));
channel->hc_num = i;
hcd->hc_ptr_array[i] = channel;
#ifdef DEBUG
Expand All @@ -1106,6 +1107,7 @@ int dwc_otg_hcd_init(dwc_otg_hcd_t * hcd, dwc_otg_core_if_t * core_if)

for (i = 0; i < num_channels; i++) {
hcd->fiq_state->channel[i].fsm = FIQ_PASSTHROUGH;
hcd->fiq_state->channel[i].hcint_handled = 0;
}
hcd->fiq_state->dummy_send = DWC_ALLOC_ATOMIC(16);

Expand Down
14 changes: 12 additions & 2 deletions drivers/amlogic/usb/dwc_otg/310/dwc_otg_hcd_intr.c
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Expand Up @@ -659,7 +659,17 @@ int32_t dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd_t * dwc_otg_hcd)
for (i = 0; i < dwc_otg_hcd->core_if->core_params->host_channels; i++) {
if (haint.b2.chint & (1 << i)) {
retval |= dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd, i);
}

// inform fiq level to know the host channel interrupt been handled
// turn on the corresponding bit in haintmsk to allow next hw intr
if (fiq_fsm_enable&&dwc_otg_hcd->core_if->use_fiq_flag &&
dwc_otg_hcd->hc_ptr_array[i]->ep_type == DWC_OTG_EP_TYPE_BULK &&
dwc_otg_hcd->fiq_state->channel[i].fsm == FIQ_PASSTHROUGH) {
local_fiq_disable();
dwc_otg_hcd->fiq_state->channel[i].hcint_handled = 1;
local_fiq_enable();
}
}
}

return retval;
Expand Down Expand Up @@ -2713,4 +2723,4 @@ int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t * dwc_otg_hcd, uint32_t num)
return retval;
}

#endif /* DWC_DEVICE_ONLY */
#endif /* DWC_DEVICE_ONLY */