This project features a behavioral-level Verilog implementation of a simplified MIPS processor. It supports a subset of standard MIPS instructions and is designed for simulation and educational purposes.
git clone https://github.com/electrify-7/MIPS_Processor.git
cd MIPS_ProcessorEnsure that you have a Verilog simulator installed. The recommended tool is Icarus Verilog, and optionally GTKWave for waveform viewing.
sudo apt update
sudo apt install iverilog gtkwavebrew install icarus-verilog
brew install --cask gtkwave-
Compile the Verilog files:
iverilog -o output AluControl.v Control.v DataMemory.v InstructionMemory.v ProgramCounter.v RegisterFile.v TestBench.v TopModule.v
-
Execute the simulation:
vvp mips_simulation
-
(Optional) View the waveform:
gtkwave dumpfile.vcd
| Instruction Type | Format | Details |
|---|---|---|
| R-Type | opcode (6) | rs (5) | rt (5) | rd (5) | shamt (5) | funct (6) |
Opcode: 000000Funct Codes:
|
| I-Type | opcode (6) | rs (5) | rt (5) | immediate (16) |
Opcodes:
|
| J-Type | opcode (6) | address (26) |
Opcodes:
|
MIPS_Processor/
├── AluControl.v
├── Control.v
├── DataMemory.v
├── InstructionMemory.v
├── RegisterFile.v
├── TopModule.v
├── TestBench.v
├── ProgramCounter.v
└── README.md- The processor is designed for simulation, not synthesis.
- You can extend the instruction set or add pipeline stages as enhancements.
- Waveform files (e.g.,
dumpfile.vcd) can be configured in the testbench.
Feel free to open issues or submit pull requests.
GitHub: electrify-7